84results about How to "Improve test yield" patented technology

A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, and in which the first and second substrates are interconnected by wire bonding, and in which the first package includes a flip-chip ball grid array package having a flip-chip in a die-down configuration. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a flip-chip in a die-down configuration, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

The invention discloses a silicone vibrating diaphragm, a receiver module and a method for processing the silicone vibrating diaphragm. Two blocks of sheet metal are integrally formed on the silicone vibrating diaphragm through injection molding, the two blocks of sheet metal are embedded in the silicone vibrating diaphragm symmetrically, and both ends of each sheet metal are provided with a first welding part and a second welding part; each first welding part is embedded in a plane part, close to a folded ring part, of the silicone vibrating diaphragm, and is used for welding a coiling tap of a voice coil on the inner side of the voice coil; each second welding part extends out of or is embedded in a fixing part of the silicone vibrating diaphragm, and is used for welding a welding pad on an outer shell; and a connecting part connecting each first welding part and the corresponding second welding part is embedded in the silicone vibrating diaphragm to form a conductive path. By adopting the technical scheme of replacing lead wires of the voice coils with the two blocks of sheet metal of the silicone vibrating diaphragm, the problem of poor listening effect caused by collision of lead wires of the voice coils can be solved thoroughly, a wire-break risk of the lead wires of the voice coils can be avoided through the sheet metal embedded in the silicone vibrating diaphragm, and the product stability is improved.

A clock gating mechanism controls power within an integrated circuit device. One or more clock gating circuits are configured to couple a system clock to a different portion of the integrated circuit device. A logic circuit applies an enabling signal to one of the clock gating circuits to control whether the system clock passes through the clock gating circuit to a portion of the integrated circuit device associated with the clock gating circuit. A plurality of scan flip-flops is configured to provide a binary code to the logic circuit, where the binary code indicates to the logic circuit that the enabling signal should be applied to the clock gating circuit. One advantage of the disclosed technique is that power droop during at-speed testing of a device is reduced without significantly increasing the quantity of test vectors or reducing test coverage, resulting in greater test yields and lower test times.

The invention discloses an RFID (Radio Frequency Identification Device) high-frequency chip four-channel test device and a method, wherein the device at least comprises a probe station, an upper computer and an RFID reader; the probe station comprises a moveable platform and a probe card; the movable platform bears a wafer to be tested and is used for providing directional movement in the directions of X-axis, Y-axis and Z-axis; a plurality of RFID high-frequency chips to be tested are regularly distributed on the wafer; a probe on the probe card is contacted with the chips during the test; the upper computer is connected with the probe station and controls the movement of the movable platform; the probe card is provided with eight probes; every two probes are in one group and are arranged in parallel; each chip to be tested corresponds to one group of probes; the upper computer is connected with the RFID reader and controls the RFID reader to send a test signal; and the signal is returned according to the chip to be tested so as to judge the test result and store the test result in a database. Due to the RFID high-frequency chip four-channel test device and the method, the test yield and test speed of products are improved, and the test cost is saved.

The invention discloses an e/LQFP (low-profile quad flat package) planar package with a grounded ring, which comprises a carrier and the grounded ring, wherein one to two IC (integrated circuit) chips are adhered to the carrier. The IC chips are connected with an inner pin through bonding wires, the inner pin is connected with an outer pin, the lower end face of the grounded ring is higher than the upper end face of the carrier, and the carrier is connected with the grounded ring through a ribbed plate. The end face, without the IC chips, of the carrier is provided with an anti-overflow ring, the grounded ring, the bonding wires, the ribbed plate and the inner pin are packaged in a plastic packaging part which is fixedly packaged on the carrier, the outer pin is positioned outside the plastic packaging part, the outer pin and the plastic packaging part are coplanar, and the lower end face of the carrier is positioned outside the plastic packaging part or packaged inside the plastic packaging part. The e/LQFP planar package with the grounded ring is produced by procedures of wafer thinning, scribing, coring, bonding and the like. Layering or shedding of a ground wire caused by making the ground wire on the carrier can be avoided, the carrier is free of silver coating, and packaging reliability is improved.

The invention relates to an IC test device which is used for testing the encapsulated IC. The IC test device mainly comprises an upper cover plate and a base which match each other. The invention is characterized in that a through hole is contained in the upper cover plate, a plurality of test probes are arranged near the through hole and used for contacting the IC, and a test spring is contained in each test probe. In addition, at least one bearing seat corresponding to the through hole in the upper cover plate is contained in the base and used for bearing the IC. At least one bearing spring is arranged between the lower part of the bearing seat and the base, the distance between the through hole and the bearing seat is smaller than the thickness of the encapsulated IC, and the coefficient of the elasticity of the bearing spring is greater than the sum of the coefficients of the elasticity of the plurality of test springs.

The invention provides a display panel, comprising a substrate, a pixel array, and a test pad. The substrate is provided with a support surface, a display district, and a circumferential line district at the periphery of the display district. The pixel array is disposed on the support surface and located in the display district. The test pad is disposed on the support surface and located in the circumferential line district. The test pad is electrically connected with the pixel array. The test pad comprises a central part and a peripheral part surrounding the central part, wherein the height of the peripheral part is greater than the height of the central part, and the peripheral part is provided with a plurality of first grooves. The first grooves are exposed out of the support surface.

The invention discloses an e/LQFP (low-profile quad flat package) stacked package with a grounded ring and a production method of the e/LQFP stacked package with the grounded ring. Two IC (integrated circuit) chips are adhered to a carrier in a stacked manner and connected with an inner pin through bonding wires, the inner pin is connected with an outer pin, the carrier is connected with the grounded ring through a ribbed plate, and the lower end face of the grounded ring is higher than the upper end face of the carrier. The lower end face of the carrier is provided with an anti-overflow ring, the grounded ring, the bonding wires, the ribbed plate and the inner pin are packaged in a plastic packaging part, the lower end face of the carrier is packaged in the plastic packaging part or positioned outside the plastic packaging parte. A wafer is thinned and scribed prior to being subjected to coring, bonding, plastic packaging and subsequent procedures to produce the e/LQFP stacked packaging part with the grounded ring. The carrier of the stacked packaging part is free of ground wire, layering caused by stress generated by making the ground wire and bonding failure of the ground wire can be avoided, and thereby reliability and testing yield of the package are improved.

An electrical test contact electrically connects a test terminal of an Integrated Circuit (IC) test assembly with an IC terminal of an IC device in an electrical interconnect assembly. The test contact is formed of electrically conductive material and includes a head portion and a foot portion. The head portion includes a first electrical contacting portion for electrically engaging an IC terminal of an IC device during use, and the foot portion includes a second electrical contacting portion for electrically engaging a test terminal of a test assembly during use. The head portion includes a head receiving portion that receives a first resiliently biasing member to retain the first resiliently biasing member in contact with the test contact. The first resiliently biasing member biases the first electrical contacting portion against the IC terminal of the IC device during use. An electrical interconnect assembly having multiple test contacts is also disclosed.

The invention relates to a multi-circle arranged IC (integrated circuit) chip packaging member, which comprises a lead frame, inner pins, an IC chip and a plastic package body. The multi-circle arranged IC chip packaging member is characterized in that the lead frame is provided with a load; the inner pins of the lead frame are arranged around the lead frame in circles; the IC chip is provided with convex points; and the convex points are connected to the inner pins. Compared with a single-row lead frame with a same area, the multi-circle arranged IC chip packaging member has the advantage ofincreasing the number of the pins of the multi-circle arranged IC chip packaging member by over 40%; the pins can be connected with the lead frame without bonding wires; and the structure is simple and reasonable. In addition, as the heat conducting distance is short, the multi-circle arranged IC chip packaging member has better thermal property; as the convex points are in direct contact with the lead frame (a substrate, the chip), the inductance and the capacitance welded inside a circuit are reduced, the signal transmission speed is high, the distortion is little, and excellent electrical property is obtained; and the thickness and the weight of a package are reduced, thus reeling and disconnecting of a bonding wire are avoided, and the yield and the reliability for testing are improved.

The invention belongs to the technical field of Internet of Things, and particularly relates to an Internet of Things test cloud platform and method, and the test cloud platform comprises: an application management module which is used for managing and auditing a test application submitted by a user, converting the test application passing the auditing into a test task, and transmitting the test task to a task management module; a task management module which is used for dividing and scheduling the test tasks, assigning the divided and scheduled test tasks to an automatic test system, and maintaining and managing the whole life cycle of the test tasks from test preparation to test completion; and a result and statistical analysis module which is used for summarizing the test results and forming a corresponding test report after the test is completed. After the test tasks are divided and dispatched, the test tasks are issued and dispatched to the corresponding automatic test systems, the execution sequence of the different test tasks is optimized, the test efficiency is improved, the test income is increased, and therefore the test management efficiency of testing the Internet of Things equipment is improved.

A testing probe including a shaft body and a plurality of claws is provided. Each cross section of the shaft body has a substantially identical shape and a substantially identical outer diameter. The claws are formed integrally with the shaft body at an end thereof. An orthogonal projection of the claws on any one of the cross sections of the shaft body is within the contour of the cross section. Contacting a solder bump on a test pad of a circuit board with the claws of the testing probe increases the test yield of the circuit board.

The invention discloses ICT clamp probe elasticity detection equipment, and relates to the technical field of detection equipment. A gantry three-axis module, a vision module and a pressure head module are arranged; the visual module is controlled by a software control system to automatically search a MARK point; the actual MARK point is compared with original coordinates to position an ICT clamp;further from coordinate positioning, points are routed according to original data, every time the upper of a probe body is reached, the pressure is measured; the problems that the labor cost is high,the misjudgment rate is high, manual operation cannot be automatic accurate, and long time manual detection causes fatigue when a maintainer judges whether the elasticity of the probe meets the requirement or not by means of personal feeling are solved. The equipment is simple in structure, easy to be compatible and interchanged, high in efficiency, safe, low in cost, high in universality and lowin development cost, the labor intensity of manual detection is reduced, the test efficiency and test yield are improved, and the equipment can be widely applied in future.

The invention discloses a probe of a cantilevel probe card (epoxide resin probe card). The technical scheme is achieved as follows: high electroconductive polymer materials, nanometer plating of which is thick in 1-20 nm, are plated on the surface of a probe point far away from 5-10mil about. The nanometer plating of the probe effectively enables the probe to have better qualities of no adhesive, high conductivity, contact force reduction and long service life through the plating process, thereby improving the test yield of washers, lowering the frequency of cleaning the probe and reducing the whole test cost.