Multi-circle arranged IC (integrated circuit) chip packaging member and producing method thereof

A technology of chip package and production method, which is applied in the direction of electrical components, electric solid devices, semiconductor devices, etc., can solve the problems that cannot satisfy ultra-thin package products, cannot meet high density, affect high-frequency applications, etc., and achieve signal transmission Fast, good thermal performance, short heat conduction distance

Active Publication Date: 2011-10-19
TIANSHUI HUATIAN TECH +1
View PDF4 Cites 7 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The current four-sided flat no-lead package cannot meet the needs of high-density, multi-I/O packaging due to fewer pins, that is, fewer I/Os. At the same time, the bonding wire is l

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Multi-circle arranged IC (integrated circuit) chip packaging member and producing method thereof
  • Multi-circle arranged IC (integrated circuit) chip packaging member and producing method thereof
  • Multi-circle arranged IC (integrated circuit) chip packaging member and producing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0053] Example 1

[0054] (1) The thickness of the wafer is reduced by 250μm

[0055] Rough grinding thickness range, from original wafer to final thickness + film thickness + 50μm, rough grinding speed 5μm / s; fine grinding thickness range, from final thickness + film thickness + 50μm to final wafer thickness + film thickness , Refining speed: 0.4μm / s, wafer thinning method is ordinary QFN thinning, 6-inch to 8-inch wafer VG-502MKⅡ8B automatic thinning machine, 8-inch to 12-inch wafer using PG300RM / TCN;

[0056] (2) Dicing

[0057] 8-inch and below wafers use DISC3350 or double blade dicing machine, 8-inch to 12-inch wafers use A-WD-300TXB dicing machine dicing machine. Apply anti-fragment, anti-crack scribing software control technology, and control the scribing feed speed to ≤10mm / s;

[0058] (3) Single chip flip-chip loading and reflow soldering

[0059] Single chip flip chip loading, using IC chip 3 with bumps, flip chip bonding is performed on a carrier frame with a thickness of 8...

Example Embodiment

[0074] Example 2:

[0075] (1) The thickness of the wafer is reduced by 250μm

[0076] Rough grinding thickness range, from original wafer to final thickness + film thickness + 50μm, rough grinding speed 2μm / s; fine grinding thickness range, from final thickness + film thickness + 50μm to final wafer thickness + film thickness , Refining speed: 0.9μm / s, wafer thinning method is ordinary QFN thinning, 6-inch to 8-inch wafer VG-502MKⅡ8B automatic thinning machine, 8-inch to 12-inch wafer using PG300RM / TCN;

[0077] (2) Dicing

[0078] Same as in Example 1;

[0079] (3) Single chip flip-chip loading and reflow soldering

[0080] Same as in Example 1;

[0081] (4) Underfill

[0082] Select materials with low thermal expansion coefficient, heat the lower filler to 80℃, use vacuum technology to underfill the bumps 4 and the pins in the frame, and finally bake the finished product after the underfill is completed in a QFN universal baking oven Bake for about 15 minutes;

[0083] (5)~(7)

[0084] ...

Example Embodiment

[0091] Example 3

[0092] (1)~(7)

[0093] Same as in Example 1;

[0094] (8) Separate pins

[0095] Separate the connecting ribs between the pins by laser cutting method, the cutting depth is 0.13μm;

[0096] (9) Electroplating

[0097] Electroplating is the same as ordinary QFN package, and 7μm pure tin is directly plated in the electroless plating system, and the baking conditions and methods after electroless plating are the same as those of ordinary QFN package.

[0098] (10) Cutting and separating products

[0099] The same as in Example 1.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention relates to a multi-circle arranged IC (integrated circuit) chip packaging member, which comprises a lead frame, inner pins, an IC chip and a plastic package body. The multi-circle arranged IC chip packaging member is characterized in that the lead frame is provided with a load; the inner pins of the lead frame are arranged around the lead frame in circles; the IC chip is provided with convex points; and the convex points are connected to the inner pins. Compared with a single-row lead frame with a same area, the multi-circle arranged IC chip packaging member has the advantage ofincreasing the number of the pins of the multi-circle arranged IC chip packaging member by over 40%; the pins can be connected with the lead frame without bonding wires; and the structure is simple and reasonable. In addition, as the heat conducting distance is short, the multi-circle arranged IC chip packaging member has better thermal property; as the convex points are in direct contact with the lead frame (a substrate, the chip), the inductance and the capacitance welded inside a circuit are reduced, the signal transmission speed is high, the distortion is little, and excellent electrical property is obtained; and the thickness and the weight of a package are reduced, thus reeling and disconnecting of a bonding wire are avoided, and the yield and the reliability for testing are improved.

Description

technical field [0001] The invention relates to the technical field of electronic information automation component manufacturing, in particular to four-sided flat leadless IC chip packaging, specifically a multi-circle arrangement IC chip package, and the invention also includes a production method of the package. Background technique [0002] In recent years, with the rapid development of portable electronic components in the field of mobile communications and mobile computers, small packaging and high-density assembly technology has been greatly developed; at the same time, a series of strict requirements have been put forward for small packaging technology, such as requirements Package dimensions should be kept as small as possible, especially if the package height is less than 1 mm. The reliability of the connection after packaging is improved as much as possible, which is suitable for lead-free soldering and effectively reduces costs. [0003] The integrated circuit pa...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H01L23/495H01L21/60
CPCH01L2224/16245
Inventor 朱文辉慕蔚李习周郭小伟
Owner TIANSHUI HUATIAN TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap