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Multi-cycle arrangement carrier-free double-integrated chip (IC) package and production method

A technology of chip package and production method, which is applied in semiconductor devices, electric solid state devices, semiconductor/solid state device manufacturing, etc., to achieve the effects of improving test yield and reliability, good electrical performance, and low distortion

Active Publication Date: 2011-11-02
TIANSHUI HUATIAN TECH +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The current four-sided flat no-lead package cannot meet the needs of high-density, multi-I / O packaging due to fewer pins, that is, fewer I / Os. At the same time, the bonding wire is long, which affects high-frequency applications.
Moreover, the general thickness of QFN is controlled at 0.82 mm to 1.0 mm, which cannot meet the needs of ultra-thin packaging products.

Method used

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  • Multi-cycle arrangement carrier-free double-integrated chip (IC) package and production method
  • Multi-cycle arrangement carrier-free double-integrated chip (IC) package and production method
  • Multi-cycle arrangement carrier-free double-integrated chip (IC) package and production method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0054] Using 8-inch to 12-inch thinning machine, adopts rough grinding, fine grinding and polishing anti-warping process, the wafer with bump chip is thinned to 250μm, rough grinding speed: 6μm / s, fine grinding speed: 1.0μm / s; the thickness of the wafer without bumps is 100μm, the rough grinding speed is 4μm / s, the fine grinding speed is 0.8μm / s, and the chip warpage prevention process is adopted;

[0055] (2), scribing

[0056] ≤8-inch wafers use DISC 3350 double-knife dicing machine, 8-inch to 12-inch wafers use A-WD-300TXB dicing machine, and the scribing speed is controlled at ≤10mm / s;

[0057] (3), on the core

[0058] For one-time chipping, IC chips with no carrier frame and bumps are used, and flip-chip chipping is adopted; for the semi-finished products of flip-chip chipping, IC chips 7 without bumps are used for secondary chipping, using AD828 / 829 For the core machine, apply glue 13QMI538 on the back of the IC chip 3 with bumps on the first layer, and then stick th...

Embodiment 2

[0081] Use 8-inch to 12-inch thinning machine, adopt rough grinding, fine grinding and polishing anti-warping process, the wafer with bump chip is thinned to 200μm, rough grinding speed: 3μm / s, fine grinding speed: 0.6μm / s; the thickness of the wafer without bumps is 100 μm, the rough grinding speed is 2 μm / s, the fine grinding speed is 0.4 μm / s, and the chip warpage prevention process is adopted;

[0082] (2), scribing

[0083] With embodiment 1;

[0084] (3), on the core

[0085] With embodiment 1;

[0086] (4), Underfill & Curing

[0087] For the semi-finished product of the secondary flip-chip, select an insulating material with a low thermal expansion coefficient α1<1, heat the underfill to 80°C, use vacuum technology to underfill the bumps and frame pads, and finally in a QFN general-purpose oven Bake the product after filling 10 for about 30 minutes;

[0088] (5), pressure welding

[0089] With embodiment 1;

[0090] (6), plastic packaging

[0091] With embodim...

Embodiment 3

[0106] Use 8-inch to 12-inch thinning machine, adopt rough grinding, fine grinding and polishing anti-warping process, the wafer with bump chip is thinned to 200μm, rough grinding speed: 3μm / s, fine grinding speed: 0.6μm / s; the thickness of the wafer without bumps is 100 μm, the rough grinding speed is 2 μm / s, the fine grinding speed is 0.4 μm / s, and the chip warpage prevention process is adopted;

[0107] (2), scribing

[0108] With embodiment 1;

[0109] (3), on the core

[0110] The first core is made of a non-carrier frame and an IC chip 3 with bumps, and the core is flipped; the second core is carried out on the back of the IC chip 3 with bumps, and the IC chip 7 without bumps and glue are used. Diaphragm 6, the back side of the IC chip 7 without bumps has been pasted with adhesive film 6 before dicing. Using a core loading machine with adhesive film bonding function, first set the substrate heating temperature according to the type of adhesive film used. Fix the IC ...

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PUM

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Abstract

The invention discloses a multi-cycle arrangement carrier-free double-integrated chip (IC) package and a production method. The package comprises a lead frame, inner leads, IC chips and a plastic package body. The inner leads of the lead frame are arranged on the four sides of the lead frame to form a plurality of cycles; one IC chip is provided with salient points, and the other IC chip is not provided with the salient points; the salient points of the IC chip with the salient points are arrange on the inner leads of the first cycle; the back of the IC chip with the salient points is provided with a die bonding adhesive; and a soldering-pan on the IC chip without the salient points is connected with the inner leads of the second cycle by weld lines to form bonding wires. Compared with the number design of the leads of a single lead frame with the same area, the number of the inner leads of the package provided by the invention is increased by over 40 percent; due to an upper face-down chip, the double-IC package has a short thermal conduction distance, relatively higher thermal properties, high signal transmission speed, low distortion and high electrical properties, and reduces the internal welding inductance and capacitance of a circuit; and a height formed by the salient points of the upper face-down chip and soldering flux is far lower than the camber of the weld line so as to avoid the wire crossing and open circuit of the weld lines and improve test yield and reliability.

Description

technical field [0001] The invention relates to the technical field of electronic information automation components manufacturing, in particular to four-sided flat leadless IC chip packaging, specifically a multi-circle arrangement carrierless dual IC chip package, and the invention also includes a production method for the package . Background technique [0002] In recent years, with the rapid development of portable electronic components in the field of mobile communications and mobile computers, small packaging and high-density assembly technology has been greatly developed; at the same time, a series of strict requirements have been put forward for small packaging technology, such as requirements Package dimensions should be kept as small as possible, especially if the package height is less than 1 mm. The connection reliability after packaging is improved as much as possible, suitable for lead-free soldering (protecting the environment) and effectively reducing costs....

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/065H01L23/495H01L23/31H01L21/98
CPCH01L2224/73265H01L2224/48247H01L2224/32145H01L2224/16245H01L2924/30107H01L2924/14H01L24/73H01L2924/00012H01L2924/00
Inventor 朱文辉慕蔚李习周郭小伟
Owner TIANSHUI HUATIAN TECH
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