Semiconductor germanium-base substrate material and preparation method thereof

Abstract

A semiconductor substrate and a method for fabricating the same are provided. The method comprises: forming a porous layer (2) on a semiconductor base sheet (1), arranging a semiconductor Ge layer (3-1) on the porous layer, with a passivation layer (4) between the semiconductor Ge layer and the porous layer, so as to form a semiconductor Ge-on-porous layer based substrate. By utilizing the low dielectric constant of the porous layer, coupling effect that the drain side acts on the channel potential via a buried layer is effectively reduced, thereby, drain induction barrier lower effect is effectively inhibited, and parasitic capacitance between the source / drain and the substrate can be reduced, so as to improve speed characteristic of devices.

Description

technical field [0001] The invention belongs to the technical field of ultra-large-scale integrated circuit manufacturing technology, and in particular relates to a germanium-based substrate material and a preparation method thereof. Background technique [0002] With the continuous reduction of device size, the degradation of carrier mobility has become one of the key factors affecting the improvement of device performance. Compared with silicon materials, germanium materials have lower effective carrier mass, higher and more symmetrical low-field carrier mobility, narrow energy band width, and are compatible with silicon CMOS processes. Therefore, germanium-based devices are A promising direction for high-speed MOSFET devices. In order to achieve better device characteristics, the preparation of germanium-based substrate materials is also one of the current hot spots. [0003] Germanium on insulator (GeOI) has become one of the focuses of industry and academia due to the...

AI Technical Summary

Problems solved by technology

However, germanium and SiO 2 The interface contact characteristics are poor, which will degrade the corresponding device performance

For SOI devices, the drain will also affect the channel potential through the buried oxide layer, so the DIBL effect will be aggravated and the device performance will be further degraded

Although reducing the thickness of the buried layer can suppress the DIBL effect, it will increase the parasitic capacitance between the source drain and the substrate, degrading the performance of the device

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