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Semiconductor device including double gate structure and method of forming such semiconductor device

A semiconductor and double-gate technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as high-K dielectric material etching-induced damage

Active Publication Date: 2015-08-19
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, conventional methods of forming dual metal gates with two different work functions require etching the metal layer over a portion of the high-K dielectric material prior to applying another metal layer, which can result in etch-induced induction of the high-K dielectric material. damage

Method used

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  • Semiconductor device including double gate structure and method of forming such semiconductor device
  • Semiconductor device including double gate structure and method of forming such semiconductor device
  • Semiconductor device including double gate structure and method of forming such semiconductor device

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Embodiment Construction

[0018] The illustrations presented herein are not intended to be actual views of any particular device or system, but are merely idealized representations used to describe the invention. In addition, common elements in the figures may maintain the same numerical designation.

[0019] figure 1 A partial cross-sectional view of a semiconductor device 10 including a double gate structure 12 including a first gate stack 14 and a second gate stack 16 is shown. The double gate structure 12 may be formed on a semiconductor substrate 18, and each gate stack 14 and 16 may include multiple stacked layers. The first gate stack 14 and the second gate stack 16 may comprise similar layers or may comprise layers having different material properties.

[0020] Semiconductor substrate 18 may include n-type field effect transistor (nFET) device region 20 and p-type field effect transistor (pFET) device region 22 separated by isolation structure 24 . For example, the isolation structure 24 can...

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Abstract

Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed.

Description

technical field [0001] Embodiments of the invention relate to semiconductor devices including one or more double gate structures and methods of forming such semiconductor devices. Background technique [0002] Semiconductor devices including dual gate structures, which include dual metal electrodes or gates on a high-K dielectric, are expected to be the basis of next generation memory devices. Next, it has become a challenge to reliably fabricate and integrate dual metal gates with two different work functions. For example, conventional methods of forming dual metal gates with two different work functions require etching the metal layer over a portion of the high-K dielectric material prior to applying another metal layer, which can result in etch-induced induction of the high-K dielectric material. damage. [0003] For the above reasons, and other reasons that will become apparent to those of skill in the art upon reading and understanding this specification, there is a n...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/31H01L21/8239H10B99/00
CPCH01L29/518H01L21/32134H01L21/823842H01L29/7831H01L29/4966H01L29/513H01L29/517H01L21/823857H01L29/78H01L29/42376
Inventor 杰德布·戈斯瓦米
Owner MICRON TECH INC