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Timing control method of physical multi-partition computer architecture

A timing control and system structure technology, applied in the direction of combining various digital computers, generating/distributing signals, etc., can solve problems such as multiple system failures and affect system reliability, and achieve the effect of ensuring reliability

Active Publication Date: 2013-07-24
烟台浪潮云计算有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Once there is a problem with any group of clock signals, timing control signals, DC power or reset signals in the hardware platform, multiple systems running on it will all fail, which greatly affects the reliability of the entire system

Method used

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  • Timing control method of physical multi-partition computer architecture
  • Timing control method of physical multi-partition computer architecture
  • Timing control method of physical multi-partition computer architecture

Examples

Experimental program
Comparison scheme
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Embodiment

[0027] When the system is divided into multiple independent multiprocessor systems or coupled into a complete computer system, the Legacy IO controller uses two different timing control methods:

[0028] Timing control for multiprocessor systems:

[0029] 1. Set the legacy IO controller of the partition through the system management unit, and activate the legacy IO controller of each partition;

[0030] 2. Each partition can be turned on and off independently. After a partition receives a power-on command, the Legacy IO controller sends an enable signal to the DC power group of the partition, and the power supplies the computing unit, storage unit, and input and output unit in the partition. Power supply, and feed back the Power good signal to the Legacy IO controller;

[0031] 3. The Legacy IO controller sends an enable signal to the clock unit of the partition, and the clock unit provides clocks to the computing unit, storage unit, and input and output unit in the partition...

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PUM

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Abstract

The invention discloses a novel timing control method of a computer architecture based on NUMA (non-uniform memory access). In a computer with multiple physical layer partitions, each hardware platform is provided with an independent power system and a clock system; and the input / output unit of each partition is provided with a LegacyIO controller, and the power sequence, clock enable and resetting system of the partition are controlled by the LegacyIO controller. Therefore, when certain partition fails, other partitions can work normally as each partition is provided with the independent timing control system, power system, clock system and resetting system, so that the system reliability is fully ensured; and simultaneously, the computer of each partition can be turned on and off independently without influencing the normall work of other partitions, thus online maintenance of the system is possible.

Description

technical field [0001] The present invention relates to a technical field of computer application, in particular to a timing control method of a physical multi-partition computer architecture. Background technique [0002] Ordinary NUMA or SMP multiprocessor architecture usually only has a unified timing, clock, power supply, and reset system. Even if virtualization technology is used to implement a multi-system architecture, each system also uses a hardware platform and only has a set of fixed timing, clock, power supply, and reset systems. Once there is a problem with any group of clock signals, timing control signals, DC power or reset signals in the hardware platform, multiple systems running on it will all fail, which greatly affects the reliability of the entire system. The general NUMA or SMP multiprocessor architecture diagram is as follows figure 1 shown. Contents of the invention [0003] The purpose of the present invention is to provide a timing control meth...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/16G06F1/04
Inventor 李博乐林楷智叶丰华王欢
Owner 烟台浪潮云计算有限公司