A Regression Test Management Method for Large Scale Integrated Circuits Based on Geometric Planning

A large-scale integrated circuit, regression testing technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of lack of test management methods, efficient testing, inability to effectively allocate computing resources, etc., to achieve optimal testing The effect of efficiency

A large-scale integrated circuit, regression testing technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of lack of test management methods, efficient testing, inability to effectively allocate computing resources, etc., to achieve optimal testing The effect of efficiency

CN102289533AInactive Publication Date: 2011-12-21HAIMEN ZHONGDE ELECTRONICS DEV CO LTD
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  • A Regression Test Management Method for Large Scale Integrated Circuits Based on Geometric Planning
  • A Regression Test Management Method for Large Scale Integrated Circuits Based on Geometric Planning
  • A Regression Test Management Method for Large Scale Integrated Circuits Based on Geometric Planning

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0021] The following demonstrates the calculation process of the method for an RTL design containing 5 modules, each corresponding to 1 regression test.

[0022] 1) Obviously N=5, the parameter c obtained by fitting the functional coverage data i , x i For: (10.3, 0.31), (9.22, 0.29), (9.65, 0.27), (9.03, 0.28), (10.1, 0.26).

[0023] 2) Also run each regression test, collect disk usage information, and obtain its fitting parameter s i ,y i They are: (15.2, 0.15), (14.3, 0.12), (14.8, 0.14), (14.6, 0.11), (15.5, 013).

[0024] 3) A small amount of changes have been made to the RTL code. A set of weighted parameters βi provided by the designer are: 0.95, 0.95, 0.9, 0.9, 1, indicating that the changes are mainly concentrated on module 5, and the functional impact on module 1 and module 2 Larger, the impact on modules 3 and 4 is weaker.

[0025] 4) The administrator tries to provide an upper limit of available total computing time T=16000s and a total disk usage upper limit ...

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Abstract

The invention discloses a method for managing the regression test of a large scale integrated (VLSI) circuit in the field of design verification and electronic design automation (EDA). According to the method, functional coverage and disk usage are modeled into the power function of time to compute a computing resource allocation solution based on a geometric programming method under the condition of limited total computing time and disk usage and obtain the optimal allocation curve of the computing resources by properly changing the total computing time limit T and the total disk usage limitS, wherein the curve is the basis for a manager to allocate computing resources for the regression test. According to the method, the efficiency of the computing resources can be maximized; the maximal function coverage can be obtained; available computing resources are effectively allocated to achieve the optimal test efficiency; the iteration of design and verification is reduced and the development period of products is shortened.

Description

technical background [0001] The invention belongs to the electronic design automation (EDA) field of large scale integrated circuit (VLSI) design verification, in particular to a regression test management method based on geometric planning. Background technique [0002] The verification work of VLSI design is of great significance to ensure the correctness of the function of the chip. In the design process of VLSI, the regression test runs throughout. VLSI design is generally described in RTL code. When the RTL code is slightly modified, all existing tests must be run repeatedly to ensure that the modification does not introduce design errors. For complex VLSI designs with multiple RTL modules, multiple verification personnel participate in the writing of regression tests, and there are many regression tests. To achieve 100% functional coverage, the regression test time is too long, and the disk usage is too large, exceeding The amount of computing resources available. On...

Claims

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Application Information

Patent Timeline
21 Dec 2011
Publication
CN102289533A
IPC
G06F17/50
Inventors
周丽明