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IBIS (Input/Output Buffer Information Specification) model verification method and system

A model verification and model technology, applied in the fields of communication and electronics, can solve the problem of inability to verify the accuracy of the model, and achieve the effect of accelerating the development progress, quality and high precision

Inactive Publication Date: 2012-01-11
ZTE CORP
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  • Abstract
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  • Claims
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Problems solved by technology

The disadvantage of this method is that its verification principle is to derive a new set of data to verify the model based on the data of the existing model. This method can verify the larger defects in the model, but it cannot verify the subtle accuracy of the model.

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  • IBIS (Input/Output Buffer Information Specification) model verification method and system
  • IBIS (Input/Output Buffer Information Specification) model verification method and system
  • IBIS (Input/Output Buffer Information Specification) model verification method and system

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Embodiment Construction

[0033] The present invention adopts following technical scheme:

[0034] A standard test circuit board is constructed for the pins corresponding to the model to be verified of the device, and the test circuit board covers as much as possible the pins corresponding to all the models to be verified on the device to ensure high utilization of the test circuit board. Use appropriate stimulus to make the corresponding pin of the model to be verified emit the required waveform, and then use a suitable instrument to capture this waveform to complete the acquisition of the verification benchmark. Construct the circuit topology model of the pins corresponding to the model to be verified on the test board circuit board in the simulation tool, and perform reflection simulation. At this time, the simulation waveform obtained by simulating according to the model to be verified can be obtained. The verification and grading of the model to be verified is completed by fitting, comparing and m...

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Abstract

The invention provides an IBIS (Input / Output Buffer Information Specification) model verification method, comprising the steps of: establishing a test circuit board specific to a pin corresponding to a model, to be verified, of a device, exciting the test circuit board, and detecting detection waveforms output by the test circuit board; establishing a circuit topological model of the pin corresponding to the model to be verified on the test circuit board, and simulating to obtain simulated waveforms; and comparing the simulated waveforms and the test waveforms and obtaining a model verification result according to a comparison result. The invention further provides an IBIS model verification system. According to the invention, the final output waveforms of the model are used to verify the quality of the model so that higher precision is achieved.

Description

technical field [0001] The invention relates to the fields of electronics and communication, in particular to a method and system for verifying the quality of an IBIS model of a digital device. Background technique [0002] In the development process of high-speed digital circuits in the electronic communication industry, signal integrity simulation technology is often used to predict hardware circuit performance or accelerate debugging progress. The premise of using signal integrity simulation technology is to obtain an accurate device model. The most widely used device model is the IBIS (I / OBuffer Information Specification, input / output buffer information specification) model. The IBIS model describes the device pins (input , output and IO buffer) behavior and electrical characteristics, does not involve the underlying structure and process information of the device, generally provided by the device manufacturer. Due to the uneven quality of the IBIS model, the characteri...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG01R31/2848G06F17/5036G06F30/367
Inventor 叶凯眭诗菊
Owner ZTE CORP
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