Semiconductor element packaging structure and manufacturing method thereof

A technology of packaging structure and manufacturing method, which is applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc.
CN102324418AInactive Publication Date: 2012-01-18ADVANCED SEMICON ENG INC
3 Cites 115 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
ADVANCED SEMICON ENG INC
Publication Date
2012-01-18
Estimated Expiration
Not applicable · inactive patent

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

The invention discloses a semiconductor element packaging structure and a manufacturing method thereof. The semiconductor element packaging structure at least comprises a tube core, a rewiring layer and a plurality of electric conduction columns in electrical connections with the rewiring layer, wherein, the tube core and the electric conduction columns are wrapped by a packaging colloid, and a plurality of inner connection patterns on the packaging colloid are in electrical connections with the electric conduction columns and a stacked second semiconductor packaging.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The invention relates to a semiconductor, and in particular to a semiconductor assembly and packaging process. Background technique

[0002] Wafer level packaging (WLP) which is widely used at present can greatly improve the packaging efficiency and reduce the size of the semiconductor package. The traditional fan-in (Fan-in) wafer-level packaging process is carried out on uncut wafers, so that the size of the final packaged product is about the same as the die size. The Fan-out wafer-level packaging process uses reconstitution wafers, that is, rearranges individual dies into artificial die-cast wafers, thereby reducing the need for expensive flip-chip substrates. Enlarge the package size with encapsulant for higher output / input (Input / Output; I / O) applications.

[0003] In the three-dimensional wafer level packaging (3-D WLP), there is a strong need for efficient and reliable electrical connection between the stacked components. Contents of the in...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More