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Packaging method and structure of chip

A packaging method and packaging structure technology, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve the problems of sharing large-area pins on the same substrate, poor temperature performance, and inability to have thermal conductivity, etc., to achieve Good heat dissipation protection, high package stability, and the effect of avoiding package deformation

Inactive Publication Date: 2012-01-25
SHANDONG SINOCHIP SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The above two methods have great disadvantages: any arrangement similar to 1) sharing the same substrate requires a large area of ​​pins
Because the chip in the middle is isolated and connected with very small leads, it cannot conduct heat very well, so its temperature performance will be poor (see figure 2 )

Method used

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  • Packaging method and structure of chip
  • Packaging method and structure of chip
  • Packaging method and structure of chip

Examples

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Embodiment Construction

[0038] The invention provides a chip packaging method, the method comprising the following steps:

[0039] 1) Chip 1 is mounted on a separate chip lead frame or substrate (lead frame 3 or substrate 4);

[0040] 2) Connect one side of the chip lead frame or substrate obtained in step 1) to the external packaging substrate 6, one or more chip lead frames or substrates.

[0041] The chip lead frame or substrate is directly used as an external package pin through the metal pins arranged on the chip lead frame or substrate through the pin hole provided on the package substrate, or the chip lead frame or substrate is connected to the soldering part of the external package through wiring. Ball 5 on.

[0042] 3) Compound filling is performed on the chip lead frame or the substrate in step 2).

[0043] When there are multiple chip lead frames or substrates, the chip lead frames or substrates are placed vertically on the plane of the external package; multiple chip lead frames or subs...

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Abstract

The invention relates to a packaging method and structure of a chip. The method comprises the following steps of: 1, installing the chip in an independent chip lead frame or substrate; and 2, connecting one side of the obtained chip lead frame or substrate to an external packaging substrate. By using the packaging method and structure of the chip, the packaging deformation can be avoided, the packaging stability is high, the electric property is good, and the application scope is wide.

Description

technical field [0001] The invention belongs to the field of electronic components, and relates to a chip packaging method, in particular to a highly reliable and high-density chip packaging method and its packaging structure. The chip packaging can be applied to any computer, notebook, workstation, and other semiconductor devices. In the electronic application of the device, high-density packaging of memory or other semiconductor chips can be achieved, that is, smaller pins, better stability, and better thermal performance. Background technique [0002] Today's computer systems use individual chip packages, either single semiconductor chip packages or so-called multi-chip packages. Today's multi-chip packages use one of the following two methods: 1) The semiconductor chips are mounted on a shared substrate, and they do not overlap in the vertical direction, which is relative to the traditional PCB board (printed circuit board). 2) Semiconductor chips are stacked on top of ...

Claims

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Application Information

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IPC IPC(8): H01L21/50H01L21/60H01L23/488
CPCH01L25/105H01L2225/1029H01L2225/1023H01L2224/32225H01L2224/32245H01L2224/49171H01L2224/48227H01L24/48H01L2924/15311H01L2224/73265H01L23/50H01L24/49H01L2224/48247H01L2224/48471H01L21/56H01L2224/48091H01L23/49537H01L25/10H01L24/73H01L2924/00014H01L2924/00012H01L2924/00H01L2224/45099
Inventor 濮必得
Owner SHANDONG SINOCHIP SEMICON
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