Packaging body formed by piling multiple chips and manufacturing method thereof

Abstract

The invention provides a packaging body formed by piling multiple chips and a manufacturing method thereof. The packaging body formed by piling multiple chips in the invention comprises a lead frame, a first chip, a second chip, a first lead, a second lead and a packaging material, wherein an opening is formed in the central part of the chip placing disk of the lead frame; the first surface of the first chip is combined to the lower surface of the chip placing disk, one part of the first surface is exposed by the opening of the chip placing disk; the first surface of the second chip is combined to a second surface opposite to the first surface of the first chip; the first lead is connected between the exposed part of the first chip and the inner pin of the lead frame; the second lead is connected between the edge of the second chip and the inner pin of the lead frame; and the packaging material can encapsulate the lead frame, the first chip, the second chip, the first lead and the second lead, so that the second surface opposite to the first surface of the second chip is exposed. The whole thickness of the packaging body is reduced, and heat dissipation property is improved.

Description

technical field [0001] The present invention relates to a semiconductor package and a manufacturing method thereof, more specifically, the present invention relates to a multi-chip semiconductor package capable of reducing the thickness of the package and improving heat dissipation performance and a manufacturing method thereof. Background technique [0002] As the simplest and most commonly used packaging technology, chip stacking is to stack and interconnect multiple chips. Due to its superior performance and relatively small footprint, multi-chip packaging will become an effective solution for semiconductor packaging technology. [0003] figure 1 is a schematic diagram showing a multi-chip package in the prior art. refer to figure 1 , the multi-chip package includes: a lead frame 1, the lead frame 1 includes external pins 11 for connecting external devices, internal pins 12 for connecting chips and chip placement pads 13 for placing chips; the first chip 2 , combined ...

AI Technical Summary

Problems solved by technology

In the structure in which multiple chips are attached to both sides of the lead frame, the complexity of the packaging process increases. Therefore, in the SMT process, this structure cannot continuously attach the chips, but after the chips on one side must be attached, the lead Flip the frame over and paste the chip on the other side

In addition, since the chip is completely encapsulated by resin, it leads to the defect of thermal performance of the package

[0005] US Patent Application No. US 6437447 discloses a multi-chip packaging structure. In this packaging structure, since there is no chip placement plate, although the overall thickness of the packaging structure is improved, but because the packaging resin encapsulates all the chips and leads, there are still defects in the heat dissipation performance of the package structure, that is, the heat dissipation performance is not good

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