FPGA (Field Programmable Gate Array) configuration circuit structure

Abstract

The invention relates to a FPGA (Field Programmable Gate Array) configuration circuit structure, which comprises a configuration memory, a configuration centre, a distributed listed address decoder, a frame data register, a derivative register, a line control circuit and a multi-channel selector. By means of the improved design of the traditional configuration circuit structure, frame structures for data configuration can be improved from the traditional longitudinal one-bit width physical distribution into the matrix type physical distribution; furthermore, matrixes of a configuration memoryunit can be addressed by using row addresses, line addresses and auxiliary addresses, so that the single independent configuration is completed. By adopting a FPGA configuration method of the circuitstructure, the frame length set for data configuration is simplified; the configuration instruction complexity level is reduced; the hardware expense is reduced; furthermore, a programmable logic module in a FPGA can be re-configured independently; an ambient programmable logic module cannot be influenced; precious configuration time is saved for dynamic reconstruction and application of users; and the flexibility of the dynamic reconstruction and application of the users can be greatly increased.

Description

technical field [0001] The invention relates to an FPGA configuration circuit architecture, in particular to an optimized configuration circuit architecture for FPGA dynamic reconfiguration, and belongs to the field of integrated circuits. Background technique [0002] figure 1 It is a simplified schematic diagram of a Field Programmable Gate Array (FPGA, Field Programmable Gate Array), such as FPGA100. Like other integrated circuits, FPGA 100 is also manufactured on a semiconductor substrate plane. Here, in order to illustrate the configuration principle of FPGA 100 for convenience, FPGA 100 is functionally divided into two levels: configuration part 120 and logic part 150 . [0003] Configuration section 120 generally includes configuration circuitry 122 and configuration memory 125 . The configuration circuit 122 includes dedicated or dual-function Pin-linked input / output interface circuits, such as boundary scan circuit (JTAG), serial-parallel configuration interface c...

AI Technical Summary

Problems solved by technology

[0009] The technical solution problem of the present invention is: overcome the inadequacy of prior art, provide a kind of FPGA configuration circuit framework, solve the traditional FPGA configuration circuit framework and can complete a programmable logic module CLB only by writing multi-frame configuration data The problem and the frame length is uncertain, which is not conducive to the problem of device scale expansion

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