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Forming method of contact hole

A technology of contact holes and dielectric layers, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problem that contact holes cannot meet the requirements of small-size technology, and achieve the effect of reducing the aperture

Active Publication Date: 2012-03-14
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] However, with the reduction of the feature size (CD) in the semiconductor manufacturing process, the feature size (CD) of the contact hole needs to be smaller and smaller, so the contact hole formed by the above-mentioned traditional method cannot meet the requirements of the small size process.

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  • Forming method of contact hole

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Embodiment Construction

[0027] It can be seen from the background technology that with the reduction of the characteristic dimension (CD) in the semiconductor manufacturing process, the characteristic dimension (CD) of the contact hole needs to be smaller and smaller. requirements.

[0028] After a lot of research, the inventor of the present invention thinks that in the etching step, as the temperature decreases, the chemical reaction slows down, so that the polymer generated in the etching process increases, and the temperature of the polymer can be controlled by controlling the etching temperature. The amount generated, and the polymer can be attached to the sidewall of the etched hole, which is beneficial to reduce the CD of the etched hole. The inventor obtained a method for forming a contact hole through the above research, wherein by dividing the etching step of the contact hole into two steps, the first step is etched at a lower first temperature, so that more polymers can be generated To re...

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Abstract

The invention provides a forming method of a contact hole, which comprises the steps that: a semi-conductor substrate is provided; the semi-conductor substrate comprises an electrode, a dielectric layer which covers the electrode and a masking layer which covers the dielectric layer; a first opening is arranged in the masking layer, and the position of the first opening corresponds to the position of the electrode; at first temperature, the dielectric layer is etched along the first opening, and a second opening is formed in dielectric layer with partial thickness; at second temperature, the dielectric layer with the rest thickness is etched along the second opening; a third opening is formed in the dielectric layer with the rest thickness; the electrode is exposed through the third opening; and the second temperature is higher than the first temperature, so that the size of the contact hole can be reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a contact hole. Background technique [0002] With the rapid development of ULSI (Ultra Large Scale Integration), the manufacturing process of integrated circuits has become more and more complex and sophisticated. In order to improve integration and reduce manufacturing costs, the critical dimensions of components are getting smaller and the number of components per unit area of ​​the chip is increasing. It is difficult for planar wiring to meet the requirements of high-density distribution. Multilayer wiring technology can only be used to take advantage of the verticality of the chip. Space, and further increase the integration density of the device. Conductive vias are required to make electrical connections between the layers of wiring. [0003] For example, a method for forming a contact hole is provided in Chinese Patent Document P...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L21/311
Inventor 韩秋华黄敬勇李国锋
Owner SEMICON MFG INT (SHANGHAI) CORP