Threshold value offset calibration method applied to time domain comparator

Abstract

The invention discloses a threshold value offset calibration method applied to a time domain comparator. The output of the time domain comparator of which the input end is short-circuited is detected, rough regulation control words for zero-crossing detection are regulated at first and then fine regulation control words for the zero-crossing detection are regulated until threshold value offset is decreased to be in a calibrated error range. The method comprises the following steps of: resetting the rough regulation control words and the fine regulation control words to be initial values, and short-circuiting the input end of the time domain comparator; regulating the rough regulation control words for corresponding zero-crossing detection according to a result of the comparator until the comparison result is changed; regulating fine regulation control words for corresponding zero-crossing detection according to the result of the comparator until the comparison result is changed; and disconnecting the input end of the comparator to finish the calibration of the threshold value offset. The method has the characteristics of not influencing the speed of the comparator, not increasing additional power consumption and only requiring once working after power-on. After the multiple cyclic feedback regulation of the control words, the threshold value offset of the comparator can be greatly decreased and a clock cycle required by the finishing of the calibration can be effectively controlled.

Description

technical field [0001] The invention relates to a threshold offset calibration method applied to a time domain comparator, which is suitable for the design of analog integrated circuits under modern advanced technology. technical background [0002] The comparator is an important module in the analog-to-digital converter, and its performance directly determines the conversion rate and precision. In order to meet the design requirements of low-voltage and low-power analog-to-digital converters compatible with modern advanced technology, a time-domain comparator based on pulse width modulation is proposed to replace the traditional voltage comparator. Although this kind of comparator has the advantages of traditional voltage comparators, it also has the limitation of threshold value offset on circuit design. In order to reduce the impact of threshold offset, the common solution is to increase the size of the device, but it will increase the power consumption, chip area and th...

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Problems solved by technology

Two representative approaches are: Compensating threshold offsets with current sources, (see references Figueiredo P.M., Cardoso P., Lopes A., Fachada C., Hamanishi N., Tanabe K. and Vital J., "A 90nm CMOS 1.2v6b 1GS / s two-step subranging ADC”, 2006 IEEE International Solid-State Circuits Conference) but will add additional power consumption; change the scaling threshold between the comparator output capacitors, (see references Giannini V., Nuzzo P., Chironi V., Baschirotto A., Van der Plas G. and Craninckx, J., "An 820μW 9b 40MS / s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS", 2008 IEEE International Solid-State Circuits Conference ) but slows down the comparison

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