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Solid-state imaging device

A solid-state imaging device and pixel technology, which is applied in image communication, TV, color TV parts, etc., can solve the problem of limited responsiveness and achieve the effect of improving responsiveness

Active Publication Date: 2012-04-04
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to realize further high-speed operation of the CMOS image sensor, there is a limitation in the responsiveness of the vertical signal line that transmits the signal read from the pixel.

Method used

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Experimental program
Comparison scheme
Effect test

no. 1 Embodiment approach

[0028] figure 1 It is a block diagram showing a schematic configuration of the solid-state imaging device according to the first embodiment.

[0029] exist figure 1 In this solid-state imaging device, there is provided a pixel array section 1-1 in which pixels PC for storing photoelectrically converted charges are arranged in a matrix in a row direction and a column direction; The row scanning circuit 2 for scanning the pixel PC in the vertical direction, the load circuit 3-1 for making the potential of the vertical signal line Vlin follow (follow) the signal read from the pixel, and the column for digitizing the signal component of each pixel PC by CDS An ADC circuit 4, a line memory 5 for storing the signal components of each pixel PC digitized by the column ADC circuit 4 for one line, a column scanning circuit 6 for horizontally scanning the pixel PC to be read out, and a control Timing control circuit 7 for timing of readout and accumulation of each pixel PC, DA converte...

no. 2 Embodiment approach

[0038] figure 2 It is a circuit diagram showing a schematic configuration of one column of the solid-state imaging device according to the second embodiment.

[0039] exist figure 2 In the pixel array section 1-1, pixels PCn and PCn+1 are provided, and photodiode PD, row selection transistor Ta, amplifier transistor Tb, reset transistor Tc, and readout transistor Td are respectively provided in pixels PCn and PCn+1. . In addition, a floating diffusion region FD (floating diffusion) is formed as a detection node at a connection point of the amplifier transistor Tb, the reset transistor Tc, and the readout transistor Td.

[0040] Further, in the pixels PCn and PCn+1, the sources of the read transistors Td are connected to the photodiodes PD, and the gates of the read transistors Td are input with the read signals READn and READn+1, respectively. In addition, the source of the reset transistor Tc is connected to the drain of the read transistor Td, reset signals RESETn and R...

no. 3 Embodiment approach

[0076] Figure 4 It is a circuit diagram showing a schematic configuration of one column of the solid-state imaging device according to the third embodiment.

[0077] exist Figure 4 In this solid-state imaging device, instead of figure 2 The pixel array section 1-2 is provided instead of the pixel array section 1-1. In the pixel array section 1-2, a pixel PCn' is provided instead of the pixel PCn.

[0078] In the pixel PCn′, read transistors Td1 to Td4 are provided instead of the read transistor Td, and photodiodes PD1 to PD4 are provided instead of the photodiode PD.

[0079] The photodiodes PD1 to PD4 are respectively connected to the readout transistors Td1 to Td4 , and one amplification transistor Tb is shared by the photodiodes PD1 to PD4 corresponding to four pixels.

[0080] Here, by sharing the amplifier transistor Tb with a plurality of pixels, the number of amplifier transistors Tb connected to the vertical signal line Vlin can be reduced, and the responsivenes...

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Abstract

The present invention relates to a solid-state imaging device capable of increasing the responsiveness of a vertical signal line for transmitting a signal read from pixels. According to one embodiment, in a pixel array unit, pixels that accumulate photoelectrically converted charges are arranged in a matrix shape. The vertical signal line transmits a signal read out from the pixels in the vertical direction. An acceleration circuit shifts the potential of the vertical signal line in advance before a signal is read out from the pixels. The acceleration control circuit controls timing for shifting the potential of the vertical signal line in advance. The timing control circuit generates a control signal for controlling the acceleration control circuit.

Description

[0001] This application claims priority based on the priority of Japanese Patent Application No. 2010-203635 filed on September 10, 2010, and the entire content of the Japanese Patent Application is incorporated in this application. technical field [0002] This embodiment relates to a solid-state imaging device. Background technique [0003] A CMOS image sensor (image sensor) can adopt a 2-step single slope ADC in order to increase the speed of a single slope ADC that converts an analog signal from a pixel into a digital signal. In this 2-step monoclinic ADC, about 7.6 times higher speed was realized. In order to achieve further high-speed operation of the CMOS image sensor, there is a limitation in the responsiveness of the vertical signal lines that transmit the signals read from the pixels. Contents of the invention [0004] The problem to be solved by the present invention is to provide a solid-state imaging device capable of improving the responsiveness of vertical ...

Claims

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Application Information

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IPC IPC(8): H04N5/335H04N5/374H04N5/378
CPCH04N5/378H04N25/78H04N25/75
Inventor 江川佳孝
Owner KK TOSHIBA
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