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Circuit simulation service testing method and system

A technology of business testing and circuit simulation, applied in the field of communication, can solve the problems of manpower and material resources, and achieve the effect of saving test resources

Active Publication Date: 2012-04-11
RAISECOM TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In the existing implementation, each channel test generally requires no packet loss for 24 hours, and it takes a lot of time to test all the N channels of E1 / T1 service ports, which requires a lot of manpower and material resources

Method used

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  • Circuit simulation service testing method and system
  • Circuit simulation service testing method and system
  • Circuit simulation service testing method and system

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Embodiment Construction

[0031] In order to make the object, technical solution and advantages of the present invention clearer, the solutions of the present invention will be further described in detail below with reference to the accompanying drawings and examples.

[0032] see figure 2 , figure 2 It is a schematic diagram of the test flow of the circuit emulation service in the embodiment of the present invention. The specific steps are:

[0033] In step 201, determine the maximum number of E1 / T1 service ports in series, N, according to the maximum delay in the link and the bandwidth of the uplink ETH, where N is an integer.

[0034] Step 202, establish a one-to-one correspondence between each E1 / T1 business on the ETH interface on the line side of the device under test and the M-way E1 / T1 business on the branch side of the device under test and adopt a consistent packet format, wherein M is not Greater than N, M is an integer.

[0035] The packet format in this step is SAToP, CESoP, TDMoIP, ...

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Abstract

The invention discloses a circuit simulation service testing method. The maximum number N of series-wound paths of an E1 / T1 service port is determined according to a maximum delay in a link and an uplink Ethernet (ETH) bandwidth. The method comprises the following steps that: one-to-one correspondence between each path of E1 / T1 service on an ETH interface on a tested equipment line side and M paths of E1 / T1 services on a tested equipment branch side is established, and a consistent encapsulation format is adopted; the M paths of the E1 / T1 service port on the tested equipment branch side are connected in series to form an M-path series-wound test channel for the E1 / T1 service port, the test channel is connected with an error code tester, and the ETH interface on the tested equipment line side is jointed with an ETH interface of the tested equipment branch side, wherein M is not greater than N, and both M and N are integers; and the error code tester simultaneously tests the M paths of the E1 / T1 service port of the ETH interface of tested equipment through the M-path series-wound test channel for the E1 / T1 service port. The invention also discloses a system based on the same inventive concept. By the method and the system, a multi-path E1 / T1 service port can be tested simultaneously, so test resources are saved.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a circuit simulation service testing method and system. Background technique [0002] When testing a channelized ETH interface, the bit error performance test of the interface is generally performed by testing one of the E1 / T1 service ports of the N channels of E1 / T1 on the channelized ETH interface. However, due to differences in physical wiring and clock transmission, etc. , each E1 / T1 of the N E1 / T1 service ports of the channelized ETH interface has its own characteristics, and only testing one or a few of them does not represent the bit error of the N E1 / T1M channels of the channelized ETH interface Performance does not mean that the N-channel E1 / T1 service ports and M-channel channels of the channelized ETH interface can send and receive packets normally, so under strict test requirements, all N-channel E1 / T1 service ports of the channelized ETH interface should be te...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/26H04B17/00H04B17/336H04B17/391
Inventor 秦萌席云龙
Owner RAISECOM TECH
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