Multi-main-bus arbitration sharing device and arbitration method

Abstract

The invention relates to a multi-main-bus arbitration sharing device, which comprises a first processor, a second processor, a complex programmable logic device (CPLD), a chip-select-line read-write-line drive device and a motherboard comprising multiple data buses, wherein after receiving a request bus event of the first and the second processors, the CPLD arbitrates the request bus event and returns an arbitration result to the first and the second processors; a processor obtaining an access priority transmits an access bus event to the CPLD; after the CPLD receives the access bus event, the access bus event is transmitted by the chip-select-line write-read-line drive device to the motherboard; after receiving the access bus event, the motherboard executes the write or read operation on the bus; after the access of the processor obtaining the access priority is ended, the bus access ending event is returned by the motherboard to the processor through the CPLD; and the processor obtaining the access priority executes the write or the read operation according to the bus access ending event so as to complete the multi-main-bus arbitration sharing operation.

Description

technical field [0001] The invention relates to the field of bus arbitration, in particular to a multi-master bus arbitration sharing device and an arbitration method. Background technique [0002] Multiple devices or modules in the system may apply for the right to use the bus at the same time. In order to avoid bus conflicts, the bus arbitration mechanism needs to reasonably control and manage the applicants who need to occupy the bus in the system. When multiple applicants submit bus requests at the same time , the bus arbitration mechanism determines the order of access to the bus based on a predetermined algorithm. [0003] A fairly common approach to traditional bus arbitration schemes is the round-robin arbitration scheme, which distributes bandwidth equally among all processing components, but completely ignores latency requirements; each processing component uses the bus according to a reasonable order, even when a certain When a processing component needs to have ...

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a multi-master bus arbitration sharing device and arbitration method, which solves the problem that the tradi

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