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Shallow trench isolation (STI) structure chemical mechanical polishing (CMP) method and STI structure manufacture method

A manufacturing method and a technology of shallow trenches, which are applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as unfavorable wafer surface flatness and increase process complexity, so as to reduce process complexity and improve flatness degree of effect

Active Publication Date: 2014-08-13
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] For this three-layer film structure, the usual STI-CMP polishing will stop on the silicon nitride (liner nitride) protective layer at the end, thus requiring additional wet The silicon nitride protective layer, the silicon oxide protective layer, and the silicon nitride barrier layer and the silicon oxide barrier layer are removed in sequence, which increases the complexity of the process and is not conducive to the flatness of the wafer surface.

Method used

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  • Shallow trench isolation (STI) structure chemical mechanical polishing (CMP) method and STI structure manufacture method
  • Shallow trench isolation (STI) structure chemical mechanical polishing (CMP) method and STI structure manufacture method
  • Shallow trench isolation (STI) structure chemical mechanical polishing (CMP) method and STI structure manufacture method

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Effect test

Embodiment 1

[0042] Referring to Fig. 1 and Fig. 2, the STI structure manufacturing method and the CMP method steps of the present invention include:

[0043]In step 1, a silicon dioxide barrier layer 2 and a silicon nitride barrier layer 3 are sequentially deposited on the silicon substrate 1; the specific deposition method can be implemented with reference to the prior art, such as the patent CN1138872C, the document "Photochemical Vapor Deposition of Silicon Nitride" Technology and Its Application Research" (Microelectronics and Computer, 1995 (3): 45).

[0044] Step 2, define shallow trench isolation regions 10 on the silicon substrate by photolithography and etching, the specific method can be implemented with reference to the prior art, such as the method disclosed in patent CN101447424B.

[0045] Step 3, sequentially depositing a silicon dioxide protective layer 4 and a silicon nitride protective layer 6 in the shallow trench to form a double inner wall protective layer;

[0046] S...

Embodiment 2

[0053] Referring to Fig. 1 and Fig. 2, the STI structure manufacturing method and the CMP method steps of the present invention include:

[0054] In step 1, a silicon dioxide barrier layer 2 and a silicon nitride barrier layer 3 are sequentially deposited on the silicon substrate 1; the specific deposition method can be implemented with reference to the prior art, such as the patent CN1138872C, the document "Photochemical Vapor Deposition of Silicon Nitride" Technology and Its Application Research" (Microelectronics and Computer, 1995 (3): 45).

[0055] Step 2, define shallow trench isolation regions 10 on the silicon substrate by photolithography and etching, the specific method can be implemented with reference to the prior art, such as the method disclosed in patent CN101447424B.

[0056] Step 3, sequentially depositing a silicon dioxide protective layer 4 and a silicon nitride protective layer 6 in the shallow trench to form a double inner wall protective layer;

[0057] ...

Embodiment 3

[0064] Referring to Fig. 1 and Fig. 2, the STI structure manufacturing method and the CMP method steps of the present invention include:

[0065] In step 1, a silicon dioxide barrier layer 2 and a silicon nitride barrier layer 3 are sequentially deposited on the silicon substrate 1; the specific deposition method can be implemented with reference to the prior art, such as the patent CN1138872C, the document "Photochemical Vapor Deposition of Silicon Nitride" Technology and Its Application Research" (Microelectronics and Computer, 1995 (3): 45).

[0066] Step 2, define shallow trench isolation regions 10 on the silicon substrate by photolithography and etching, the specific method can be implemented with reference to the prior art, such as the method disclosed in patent CN101447424B.

[0067] Step 3, sequentially depositing a silicon dioxide protective layer 4 and a silicon nitride protective layer 6 in the shallow trench to form a double inner wall protective layer;

[0068] ...

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Abstract

The invention discloses an STI-CMP method for a silicon oxide / silicon nitride double inner wall protective layer and a method for manufacturing an STI structure by using the method, using a method with a higher grinding rate ratio of silicon oxide to silicon nitride Grinding and removing the silicon dioxide filling layer of the groove and stopping on the silicon nitride protective layer, and then polishing the silicon nitride protective layer with a polishing slurry with a higher silicon nitride to silicon oxide grinding rate ratio, and completely removing After the silicon nitride protective layer is formed, the silicon dioxide protective layer is polished with the original polishing fluid having a relatively high polishing rate ratio of silicon oxide to silicon nitride, and finally stays on the silicon nitride barrier layer. Therefore, the additional wet etching step of removing the silicon nitride protective layer and the silicon dioxide protective layer in the traditional STI manufacturing method is avoided, the process complexity is reduced, and the flatness of the wafer surface is improved.

Description

technical field [0001] The present invention relates to a manufacturing process of electronic components, in particular to a chemical mechanical polishing method for a shallow trench isolation structure of a silicon oxide / silicon nitride double inner wall protective layer, and using the method to manufacture the shallow trench isolation structure Methods. Background technique [0002] In a semiconductor manufacturing process, shallow trench isolation (Shallow Trench Isolation, or STI) technology is widely used as a device isolation technology. As shown in Figure 1, the common STI process flow is: first deposit a layer of silicon oxide (pad oxide) and silicon nitride (pad nitride) on a silicon substrate (substrate) 1 in sequence, where the silicon oxide layer is used as the silicon lining The bottom protective layer, silicon nitride as a barrier layer for subsequent etching and chemical mechanical polishing processes ( Figure 1a ). Then through photolithography and etching...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/3105H01L21/762
Inventor 方精训邓镭
Owner SHANGHAI HUALI MICROELECTRONICS CORP