Method for forming single Damascus of thick metal
A thick metal and thicker metal technology, applied in the field of single damascene forming thick metal, can solve the problems of unfavorable etching process etching shape and size, reduce interconnect reliability, increase sheet resistance, etc., to reduce chip The effect of interconnecting sheet resistance, reducing process complexity, and reducing signal delay
Active Publication Date: 2014-12-10
SHANGHAI HUALI MICROELECTRONICS CORP
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Problems solved by technology
Because the thickness is too thick, it means that the depth of the trench structure is very large, which will not be conducive to the etching process to control the shape and size of the etching, and the metal filling process is also difficult to complete the complete filling, which will increase the sheet resistance and reduce the interconnection. reliability, with a very detrimental effect on the
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[0030] The present invention provides a single damascene method of forming thick metal. Using a single damascene process to add the bottom half of the copper interconnect that needs to reduce the sheet resistance in the via layer, this layer requires two photolithographic etching processes. Subsequent metal filling and chemical mechanical polishing results in a first portion of copper interconnects with reduced sheet resistance. Metal trenches are then constructed using a single damascene process, and the trench thickness is the same for all metal wires in this layer. Due to the alignment relationship between the upper and lower layers, there are copper interconnections pre-set in the first layer under some metal wires. Therefore, compared with ordinary interconnections, this part of copper interconnections has a thicker metal thickness. , or there are two interconnection lines in parallel, so a lower sheet resistance is obtained.
[0031] In order to obtain high performance...
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Abstract
The invention provides a method for forming a single Damascus of thick metal. An additional metal interconnection for reducing copper interconnection sheet resistance is added in a through hole layer through the single Damascus process; a through hole structure and an addition abundant metal interconnection are merged in the same optical mask so as to reduce process complexity; a final structure can be finished by only twice photoetching processes; and the through hole structure and the addition abundant metal interconnection are combined with copper metal wires at the next layer of the single Damascus so as to finally obtain copper interconnection wires with lower sheet resistance. Through the method provided by the invention, the depth of a copper interconnection wire trench can be selectively changed so as to reduce the sheet resistance of the copper interconnection wires which meet conditions and are in a specified region and selectively reduce the chip interconnection sheet resistance. Under the condition of not changing the whole copper interconnection depth, not increasing process difficulty, and not reducing a process window, the interconnection sheet resistance is reduced to a maximum extent so as to reduce a signal delay of the chip, reduce loss and improve the integral performance of the chip.
Description
technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a single damascene method for forming thick metal. Background technique [0002] In the semiconductor integrated circuit industry, high-performance integrated circuit chips require high-performance back-end electrical interconnections. Due to the low resistivity properties of metal copper, it has been more and more widely used in advanced integrated circuit chips. From aluminum wires to copper wires, the change in material has brought about a huge reduction in resistivity. With the advancement of integrated circuit technology, the complexity of the chip increases, and the complexity and length of the back-end interconnection become larger and larger, which means that the resistance of the back-end interconnection line in the chip becomes one of the performance bottlenecks. Effectively reducing resistance has become an important research topic in integrated circuits. ...
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IPC IPC(8): H01L21/768H01L21/3205
Inventor 姬峰张亮胡友存李磊陈玉文
Owner SHANGHAI HUALI MICROELECTRONICS CORP