Method, device and system for realizing packet reorganization by adopting accelerating technology

Abstract

The invention relates to a method, device and system for realizing packet reorganization by adopting an accelerating technology. The method comprises the following steps of: receiving cells from an exchange board and separating head spending parts and net load parts of the cells by an outlet wire clamp; storing net loads of the cells in a cache of the outlet wire clamp according to the head spending parts; sending accelerating cell information to the exchange board when cache utilization of the outlet wire clamp exceeds a set threshold, so that the exchange board can look for a corresponding accelerating cell from the cache according to the accelerating cell information and send the corresponding accelerating cell to the outlet wire clamp as a corresponding cell; and reorganizing and sending data packets by the outlet wire clamp so as to release a cache space occupied by the data packets. In the invention, a cell sending sequence in the exchange board is controlled by using the accelerating technology, and all exchange boards can synchronously send the cells of the same data packet as quick as possible, so that packet reorganization difficulty, exchange time delay and delay jitter of the outlet wire clamp are reduced, expandability of an exchanging network is promoted, and maximum exchange capacity of the same is increased.

Description

technical field [0001] The present invention relates to the field of communication technology, in particular to a method, device and system for realizing packet reassembly by adopting an acceleration technology. Background technique [0002] The existing switching network includes two parts: line cards and switching boards, and the line cards are divided into ingress line cards and egress line cards, such as figure 1 As shown in , it is a schematic diagram of the basic structure of the switching network in the prior art. [0003] At present, high-speed routers usually use a fixed-length cell switching mechanism to split data packets arriving at the switching network into multiple fixed-length cells. Cells can reach the egress line card through different switching boards. Since the time delays for cells passing through different switching boards may be different, the cells originally belonging to a data packet will arrive at the egress line card in a chaotic order. [0004...

AI Technical Summary

Problems solved by technology

Although out-of-sequence cells can be reorganized into data packets in the end, the size of the buffer space used is proportional to the number N of ingress line cards, which is difficult to achieve in a packet-switched network with large switching capacity.

In addition, this scheme is the same as (1), without improving the performance of delay and jitter, and the implementation is quite complicated

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