Memory device and method of fabricating the same

Abstract

The present invention provides a memory device and a method of fabricating the same. The memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source / drain regions and at least one channel base region corresponding to the paired source / drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region. The word lines of the memory device in the present invention can be isolated properly with each other, so as to avoid interference between the word lines. In addition, the word lines are arranged in a vertial direction, so that the width of the word line is increased, so as to reduce resistance of the word line.

Description

technical field [0001] The present invention relates to a memory device, in particular to a memory device with a trench cell structure and a manufacturing method thereof. Background technique [0002] Due to its simple structure, dynamic random access memory (DRAM) can provide more memory cells per unit chip area than other types of memory, such as static random access memory. A dynamic random access memory includes a plurality of random access memory cells, and each random access memory cell includes a capacitor for storing data and a transistor, wherein the transistor is coupled to the capacitor to control its charge and discharge. During a read operation, a word line is actuated to turn on the transistor. The on-transistor enables the voltage across the capacitor to be read by a sense amplifier through a bit line. During a write operation, when a word line is actuated, the data to be written is provided on the bit line. [0003] In order to meet the demand for better m...

AI Technical Summary

Problems solved by technology

[0004] However, when the size of memory cells shrinks, many problems arise

For example, interference between memory cells or between word lines can easily

As the cross-sectional area of ​​the word line decreases, the resistance of the word line increases

In addition, the reduction of capacitance and bit line contact area increases the contact resistance

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