Method and system for verifying register transfer level (RTL) of Ethernet exchange chip queue manager

A technology for exchanging chips and verification methods, which is applied in the field of computer networks, can solve the problems of difficult positioning and error checking, low verification efficiency, difficulty in automatic and accurate detection of output traffic, etc., and achieves the effect of improving efficiency

Active Publication Date: 2012-06-13
SUZHOU CENTEC COMM CO LTD
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Problems solved by technology

However, due to the long establishment time of the hardware simulation platform, it is very difficult to locate problems and troubleshoot, and the existing RTL software simulation methods are difficult to accurately generate input traffic for the behavior of the queue manager, and it is difficult to automatically and accurately detect output traffic behavior, and the verification efficiency is relatively low. the disadvantages of

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  • Method and system for verifying register transfer level (RTL) of Ethernet exchange chip queue manager
  • Method and system for verifying register transfer level (RTL) of Ethernet exchange chip queue manager
  • Method and system for verifying register transfer level (RTL) of Ethernet exchange chip queue manager

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Embodiment Construction

[0029] The technical solutions in the preferred embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention.

[0030] An RTL-level verification method for an Ethernet switch chip queue manager disclosed by the present invention is used to test and control the quantity, type, sequence and bandwidth of input streams in Ethernet. Before testing, a chip-based RTL verification method must first be built. Level simulation verification environment, and then set up the stimulus for testing and the model for test detection in the simulation verification environment. The simulation verification environment in this embodiment is built with the hardware language verilog.

[0031] Test stimuli can generate different types of data flows, each flow contains data packets with different priorities, test stimuli can freely control the number and sequence of data packets, and the bandwidth of each flow ...

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Abstract

The invention discloses a method and a system for verifying register transfer level (RTL) of an Ethernet exchange chip queue manager. The verifying method combines the advantages of an existing hardware simulation platform and a software simulation platform. By constructing a simulation environment, a testing stimulus model and a testing detection model which generate a testing stream are built to control amount, varieties, sequence and bandwidth of an input stream, a dynamic bandwidth adjustor is used for correcting the bandwidth in real time, and simultaneously the testing detection model automatically detects bandwidth which outputs different streams and provides detection results, thereby detecting whether queue scheduling and reshaping function are right in real time in a simulation process, improving verifying efficiency, and finding code defects timely and effectively.

Description

technical field [0001] The invention relates to computer network technology, in particular to an RTL (Register Transfer Level, Register Transfer Level) verification method for network traffic management by a queue manager in an Ethernet switch chip. Background technique [0002] In an Ethernet switch chip, a queue manager is a module that manages traffic congestion on the Ethernet. When the flow in the ingress direction of the chip is greater than the flow in the egress direction, the data packets in the queue are congested and need to be queued to go out, and the queue manager starts to play a role. The queue manager module is divided into four parts according to the functions: queue queuing, queue scheduling, traffic shaping and egress resource management. [0003] With the continuous enhancement and expansion of the functions of the Ethernet switch chip queue manager, and each part will involve very complex logic operations and operations, the RTL-level simulation and ve...

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Application Information

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IPC IPC(8): H04L12/26
Inventor 郑海东许俊龚源泉
Owner SUZHOU CENTEC COMM CO LTD
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