Hardware-software partitioning method based on greedy simulated annealing algorithm

A simulated annealing algorithm, software and hardware partitioning technology, applied in the direction of resource allocation, multi-programming device, etc., can solve the problems of reducing the approximate optimal solution, long algorithm running time, long initial training process, etc., to increase the search probability, Increased probability, effect of faster convergence

Inactive Publication Date: 2012-06-20
HUNAN UNIV
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Problems solved by technology

These algorithms have achieved certain results in their respective fields, but most of the existing methods combine two heuristic algorithms for hardware and software division, and it is difficult to avoid problems such as the difficulty in determinin

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  • Hardware-software partitioning method based on greedy simulated annealing algorithm
  • Hardware-software partitioning method based on greedy simulated annealing algorithm
  • Hardware-software partitioning method based on greedy simulated annealing algorithm

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Embodiment Construction

[0025] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0026] Such as figure 1 As shown, the present invention is based on the software and hardware division method of greedy simulated annealing algorithm, and its flow process is:

[0027] (1) The software and hardware division problem is reduced to a 0-1 knapsack problem, and a greedy algorithm with low time complexity is used to initially divide the task set, and then the division result is used as the initial value of the simulated annealing algorithm, so that the simulated annealing algorithm At the beginning of the search, it can approach the area where the global approximate optimal solution is located, reducing the running time of the algorithm.

[0028] (2) Simulated annealing algorithm: It is mainly composed of two layers of loops. The inner loop generates new partitions according to the disturbance model and uses the improved a...

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Abstract

A hardware-software partitioning method based on a greedy simulated annealing algorithm comprises the following steps: (1) specifying the hardware-software partitioning problem as 0-1 knapsack problem, initially partitioning a task set by a greedy algorithm with low time complexity, and setting the partitioning result as the initial value of the simulated annealing algorithm; and (2) performing the simulated annealing algorithm, which is mainly composed of two layer loops, namely an inner loop and an outer loop, wherein the inner loop can generate a new partition according to a disturbance model, and determine and accept the new partition according to an acceptance criteria; and the outer loop is used for determining whether or not to exit the loop process according to a temperature threshold and the number of new partitions which are not accepted continuously. The method provided by the invention can reduce algorithm operation time, improve search quality and reduce calculation complexity.

Description

technical field [0001] The invention mainly relates to the field of embedded system design, in particular to a method for dividing software and hardware based on a greedy simulated annealing algorithm. Background technique [0002] The division of software and hardware refers to the determination of the implementation of each module during system design to solve the mapping problem of system function modules. The partitioning of software and hardware is a key step in the co-design of embedded system software and hardware, and the result of partitioning directly determines the quality of the system design. Its basic goal is: under the condition of satisfying the design constraints, the tasks are reasonably divided into software or hardware processing units for execution, so as to achieve the optimization of system goals, specifically including the minimum hardware implementation area or the minimum running time of functional modules. According to different target architectur...

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Application Information

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IPC IPC(8): G06F9/50
Inventor 李蕊杨志邦王奕徐成刘彦黄兵骆伟张婷王辉
Owner HUNAN UNIV
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