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Hardware-software partitioning method based on greedy simulated annealing algorithm

A simulated annealing algorithm, software and hardware partitioning technology, applied in resource allocation, multi-programming devices, etc., can solve problems such as finding an approximate optimal solution, long algorithm running time, long initial training process, etc., and achieve increased probability , to speed up the convergence speed and increase the search probability effect

Inactive Publication Date: 2014-05-21
HUNAN UNIV
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Problems solved by technology

These algorithms have achieved certain results in their respective fields, but most of the existing methods combine two heuristic algorithms for hardware and software division, and it is difficult to avoid problems such as the difficulty in determining the initialization parameters of the heuristic algorithm and the long initial training process.
Improper handling of these issues can lead to excessively long running times of the algorithm and reduce the probability of finding a near-optimal solution

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  • Hardware-software partitioning method based on greedy simulated annealing algorithm
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  • Hardware-software partitioning method based on greedy simulated annealing algorithm

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Embodiment Construction

[0025] The present invention will be further described in detail below with reference to the drawings and specific embodiments of the specification.

[0026] Such as figure 1 As shown, the software and hardware partition method of the present invention based on the greedy simulated annealing algorithm, the process is:

[0027] (1) The software and hardware division problem is reduced to a 0-1 knapsack problem, and the task set is initially divided by a greedy algorithm with low time complexity, and then this division result is used as the initial value of the simulated annealing algorithm to make the simulated annealing algorithm At the beginning of the search, it can approach the area where the global approximate optimal solution is located, reducing the running time of the algorithm.

[0028] (2) Simulated annealing algorithm: It is mainly composed of two layers of loops. The inner loop generates new divisions based on the disturbance model and adopts improved reception criteria t...

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Abstract

A hardware-software partitioning method based on a greedy simulated annealing algorithm comprises the following steps: (1) specifying the hardware-software partitioning problem as 0-1 knapsack problem, initially partitioning a task set by a greedy algorithm with low time complexity, and setting the partitioning result as the initial value of the simulated annealing algorithm; and (2) performing the simulated annealing algorithm, which is mainly composed of two layer loops, namely an inner loop and an outer loop, wherein the inner loop can generate a new partition according to a disturbance model, and determine and accept the new partition according to an acceptance criteria; and the outer loop is used for determining whether or not to exit the loop process according to a temperature threshold and the number of new partitions which are not accepted continuously. The method provided by the invention can reduce algorithm operation time, improve search quality and reduce calculation complexity.

Description

Technical field [0001] The present invention mainly relates to the field of embedded system design, and specifically refers to a method of software and hardware division based on a greedy simulated annealing algorithm. Background technique [0002] Software and hardware division refers to determining the implementation of each module during system design to solve the mapping problem of system function modules. Software and hardware division is a key step in the collaborative design of embedded system software and hardware, and the division result directly determines the pros and cons of the system design. Its basic goal is to reasonably divide tasks into software or hardware processing units for execution under the conditions of meeting design constraints to achieve the optimization of system goals, including the smallest hardware realization area or the smallest running time of functional modules. According to the different target architectures, the software and hardware partit...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/50
Inventor 李蕊杨志邦王奕徐成刘彦黄兵骆伟张婷王辉
Owner HUNAN UNIV
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