Overlay specification verification method

Abstract

The invention provides an alignment specification verification method which comprises the following steps of: firstly, maintaining offsets in the X / Y directions in an optimization parameter unchangeable, adding a rotation offset, an orthogonality offset, scaling offsets in the X / Y direction additionally during exposure to ensure that deviations of second orders on different positions of the same wafer are inconsistent relative to the deviations of first orders; secondly, controlling numerical values of the additionally-added parameters to obtain an offset range required by alignment verification; and thirdly, verifying the alignment specification of a product according to the offset range. Compared with the prior art, the alignment specification verification method has the beneficial effects of reducing cost and workload due to the adoption of only one wafer, and ensuring accuracy of the alignment specification verification because the wafer is not influenced by multiple devices and multiple cavities of the same subsequent process.

Description

technical field [0001] The invention relates to an overlay specification verification method, in particular to an overlay specification verification method in integrated circuit production. Background technique [0002] In the production of integrated circuits, although the overlay specification of the product is defined in the design rules, it must be verified according to the actual situation of the production line. The method is to prepare multiple wafers with different overlay offsets, and confirm the appropriate overlay specification according to the final yield. [0003] Stacking of two levels in semiconductor production such as figure 1 As shown, under ideal conditions, the first layer 10 and the second layer 20 should completely overlap, but in fact, there will always be an overlay deviation. In order to verify the maximum deviation allowed by the product, it is necessary to prepare a lot of overlay offsets. The wafer is used to verify the yield corresponding to di...

AI Technical Summary

Problems solved by technology

[0004] 1. It is necessary to prepare multiple wafers for slicing, and apply different offsets to each wafer during exposure, which increases the usage of wafers and the workload on the production line;

[0005] 2. The same process of the production line usually has multiple devices or multiple cavities, so multiple devices / empty bodies have a potential impact on the yield of wafers, which interferes with the analysis of the corresponding relationship between overlay offset and yield

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