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Line Width Test Structure

A technology for testing structure and line width, which can be used in electrical components, electrical solid devices, circuits, etc., and can solve problems such as stacking deviation

Active Publication Date: 2016-01-20
CSMC TECH FAB2 CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Then, when the hole and active area are properly overlaid, the hole is overlaid outside the poly edge causing an overlay misalignment problem

Method used

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Embodiment Construction

[0031] The plane view of the line width test structure of the present invention is as follows Figure 5 shown, please combine Figure 5 legend in and Image 6 , the line width testing structure has an active area at the bottom layer with a certain height, a polycrystal embedded in the center of the active area and protruding from the upper surface of the active area at a certain height, and four square holes. The active area and the polycrystalline form have steps. The center of the hole overlaps with the four sides of the polycrystal, and the distance between the outer edge and the edge of the active area pattern is the minimum dimension in the design rule. Thus, each hole is registered to both the active area and the poly.

[0032] When testing, the line width is measured with a scanning electron microscope, the measurement principle is to use a focused electron beam to bombard the surface of the sample with the line width structure of the present invention to generate se...

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Abstract

The invention discloses a line width test structure. The test structure comprises a current layer and a front layer arranged below the current layer. A photo-etching graph of the current layer is designed in that the center of the photo-etching graph is positioned at the stage of the current layer. According to the line width test structure, the line width and the alignment overlaying deviation are tested at the same time by the secondary electronic imaging principle of the line width test structure.

Description

【Technical field】 [0001] The invention relates to a line width test structure, in particular to a line width test used in semiconductor manufacturing. 【Background technique】 [0002] Overlay testing is a basic process in the photolithography process of semiconductor manufacturing, and it is used to characterize the quality of two photolithography stack pairs. The implementation method is to place a specific test structure in the dicing groove, use an overlay tester to measure, and finally judge whether the overlay meets the specification according to the measured value. [0003] The overlay test structure is a test pattern specially placed in the scribe groove, and its design is as follows: figure 1 shown. The dark outer frame 1' is generally the mark left by the pattern of the previous layer, while the light inner frame 2' is the photoresist pattern of the current layer. The calculation formula for overlay is: overlay measurement value = (a-b) / 2. [0004] This method is...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544
Inventor 黄玮
Owner CSMC TECH FAB2 CO LTD
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