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Layout design used for preventing static electricity from damaging reliability sample

A technology of layout design and electrostatic destruction, applied in the direction of circuits, electrical components, electric solid devices, etc., can solve the problem that the device samples are susceptible to electrostatic damage, etc., and achieve the effect of reducing the possibility of electrostatic damage

Inactive Publication Date: 2012-07-25
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to provide a layout design for preventing static electricity from destroying reliability samples, so as to solve the problem that existing device samples are easily damaged by static electricity

Method used

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  • Layout design used for preventing static electricity from damaging reliability sample
  • Layout design used for preventing static electricity from damaging reliability sample
  • Layout design used for preventing static electricity from damaging reliability sample

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Embodiment approach

[0018] In the first embodiment of the present invention, please continue to refer to image 3 and Figure 4 shown. The above-mentioned device under test 1 includes a source 2 and a drain 3 , so that the gate capacitance 6 connected in parallel with the gate 4 will not affect the saturation current of the drain 3 of the device 1 .

[0019] In the second embodiment of the present invention, the device under test 1 is also connected in series with a base 5, so that the gate capacitance 6 connected in parallel with the gate 4 is applied to the voltage of each terminal of the device 1 gate 4, base 5, etc. without changing. .

[0020] To sum up, using the layout design of the present invention for preventing static electricity from damaging reliable samples greatly reduces the possibility of electrostatic damage to devices. At the same time, it will not affect the drain current, and normal testing can be performed.

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Abstract

The invention discloses a layout design used for preventing static electricity from damaging a reliability sample, which includes a to-be-detected packaging-level device. The device is provided with a grid electrode which is connected with a large-area gate capacitor, and static charge is shunted by the aid of the gate capacitor so as to protect the device. By the aid of the layout design used for preventing the static electricity from damaging the reliability sample, the possibility that the device is damaged by the static electricity is greatly reduced, current of a drain electrode is unaffected, and normal test can be carried out.

Description

technical field [0001] The invention relates to a reliability test structure layout, in particular to a layout for protecting packaging-level reliability test samples and reducing the influence of static electricity on the samples. Background technique [0002] figure 1 is a schematic diagram of a common device, figure 2 For common device simulation circuit diagrams, please refer to figure 1 and figure 2 shown. A device under test 1 is included, and the device 1 has a source 2 , a drain 3 , a gate 4 and a base 5 . The current samples used for reliability experiments of the device 1 are all of a single device structure, and the area of ​​the gate 4 (<10um*0.1um) is very small due to the limitation of technical specifications. When subjected to static electricity, a large current (but a small amount of electricity) is passed through in a very short time, causing the grid 4 to be burned out. In particular, the reliability test also needs to be packaged, and the elect...

Claims

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Application Information

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IPC IPC(8): H01L23/60
Inventor 尹彬锋王炯周柯
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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