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depletion mode mos transistor

A MOS transistor, depletion-mode technology, used in semiconductor devices, electrical components, circuits, etc., can solve problems such as easy breakdown, large difference between gate and drain voltage, and poor reliability.

Active Publication Date: 2016-12-07
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] In this case, in order to turn off the depletion mode MOS transistor (non-conducting), a large negative gate bias is required, which results in a large voltage difference between the gate and drain
The depletion type MOS transistor according to the prior art is prone to breakdown and has poor reliability due to a large voltage difference between the gate and the drain due to the turn-off of the depletion type MOS transistor according to the prior art

Method used

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Examples

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Effect test

no. 1 example

[0028] figure 2 The structure of a depletion MOS transistor according to the first embodiment of the present invention is schematically shown.

[0029] Such as figure 2 As shown, the depletion type MOS transistor according to the first embodiment of the present invention includes a source 31 and a drain 32 arranged in a substrate 2 (more specifically, it may be arranged in a well 21 of the substrate 2). A lightly doped region is arranged above one of the source electrode 31 and the drain electrode 32, and a lightly doped region is not arranged above the other of the source electrode 31 and the drain electrode 32. More specifically, the source lightly doped region 41 may be arranged above the source electrode 31, and the drain lightly doped region 42 is not arranged above the drain electrode 32; or alternatively, the source electrode 31 is not arranged above the source electrode 31. The extremely lightly doped region 41, but the drain lightly doped region 42 is arranged above th...

no. 2 example

[0042] image 3 The structure of a depletion mode MOS transistor according to the second embodiment of the present invention is schematically shown.

[0043] In the first embodiment according to the present invention,

[0044] Such as image 3 As shown, in the second embodiment according to the present invention, the second conductive channel 52 covers the drain 32 and the area between the source 31 and the drain 32 in the direction of channel conduction. That is, when forming the second conductive channel 52 of the depletion MOS transistor according to the second embodiment of the present invention, the drain 32 and the region between the source 31 and the drain 32 are doped.

no. 3 example

[0046] Figure 4 The structure of a depletion MOS transistor according to the third embodiment of the present invention is schematically shown.

[0047] Such as Figure 4 As shown, in the third embodiment according to the present invention, the second conductive channel 52 only covers the area between the source 31 and the drain 32 in the direction of channel conduction. That is, when forming the second conductive channel 52 of the depletion MOS transistor according to the third embodiment of the present invention, only the region between the source 31 and the drain 32 is doped.

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Abstract

The invention provides a depletion-mode metal oxide semiconductor (MOS) transistor, which comprises a source and a drain which are arranged in a substrate, a grid which is arranged above the substrate at a position between the source and the drain, a first conducting channel which is arranged in the substrate at a position below the grid, and a second conducting channel which is arranged in the substrate at a position between the source and the drain, wherein a light-doped zone is arranged above one of the source and the drain and is not arranged above the other one of the source and the drain; and the first conducting channel is next to the grid, the second conducting channel is next to the first conducting channel and the second conducting channel is next to the other one of the source and the drain. The doping concentration of the first conducting channel is larger than the doping concentration of the second conducting channel.

Description

Technical field [0001] The present invention relates to the field of semiconductor design and manufacturing. More specifically, the present invention relates to a depletion mode MOS transistor. Background technique [0002] A MOS transistor is an abbreviation for a transistor with a Metal-Oxide-Semiconductor structure. To distinguish from the type of conduction channel, MOS transistors are divided into P-type MOS transistors and N-type MOS transistors. From the relationship between channel and voltage, MOS transistors are divided into depletion MOS transistors and enhancement MOS transistors. [0003] figure 1 The structure of a depletion-type MOS transistor according to the related art is schematically shown. [0004] Such as figure 1 As shown, the depletion type MOS transistor includes: a source 31 and a drain 32 arranged in a well 21 in a substrate 2, a gate 1 arranged between the source 31 and a drain 32 above the substrate 2, and A conductive channel 51 arranged between the s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06H01L29/10H01L29/78
Inventor 吴小利唐树澍苟鸿雁
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP