Address jump output device and method

Abstract

The invention discloses an address jump output device. The device comprises a cycle counter module, a multiplexer module, a control module and an address output module; wherein the cycle counter module outputs a count value to the multiplexer module; the control module outputs a control command to the multiplexer module so as to control the operation of the count value, and finally, the operation result of the multiplexer module is output to the address output module. With the adoption of the technical scheme, the design cost can be effectively reduced, and the resource consumption and error probability of the jump circuit are reduced.

Description

Technical field [0001] The invention relates to an address jump output device and method. Background technique [0002] At present, in chip circuit design, address jump is a frequently encountered problem. Many times, different address jump methods are required in different parts of the circuit. For example, the first part needs to jump to addresses according to 0,64,128,192,1,65,129,193..., while the second part becomes according to 0,16,32, 48, 1, 17, 33, 49... Jump like this. In the traditional solution, different parts of the circuit will be counted in different ways to achieve the required jump effect. But in this way, each part needs to make different counting condition judgments, which is very troublesome and easy to conflict and make mistakes. For example, the address generation circuit mentioned in the CN102160032A patent, which sets the block size and skip size, is essentially based on a judgment of the skip condition, and this approach does not reduce the complexity...

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Problems solved by technology

But in this way, each part needs to make different counting condition judgments, which is very troublesome and prone to conflicts and errors

For example, the address generation circuit mentioned in the CN102160032A patent, which sets the block size and jump size, is essentially based on a judgment on the jump condition, and this approach does not reduce much complexity.

Another example is the "effective address = (segment + displacement) + base address + (change * ratio)" mentioned in the CN101027633A patent. occasion

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