Carry-saving multiplier

Abstract

The invention discloses a carry-saving multiplier, relating to the technical field of integrated circuit. Through analysis on the conventional carry-saving multiplier, full adders at two special positions in an array can be logically simplified, so that the speed and the power consumption are optimized on the premise of reducing the area of the multiplier; and furthermore, in an AND gate array for generating a partial product, each row of AND gates has a common signal, so that the number of transistors is reduced by sharing a downwardly drawn NMOS (N-channel Mental-oxide-semiconductor) tube; therefore, in combination of the two ways, a novel simplified carry-saving multiplier is constructed. A simulating result shows that compared with the conventional carry-saving multiplier, the carry-saving multiplier disclosed by the invention can reduce a power consumption delay product as high as 12.41 percent; the improved carry-saving multiplier still has the advantage of structural regularity of all array multiplier, so that the improved carry-saving multiplier is still applicable to design of a large-scale integrated circuit; and meanwhile, due to advantages in the speed and the power consumption of the improved carry-saving multiplier, performance of a circuit system can be further improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a carry-save multiplier. Background technique [0002] Multiplication [1] is the most basic and important operation in digital signal processing. The speed and power consumption of the multiplier will largely determine the performance of the entire circuit system. A multiplier generally consists of three parts: partial product generation, partial product compression, and a final adder chain [2]. Partial products can be generated directly through an AND gate array, or can be generated through a special algorithm (such as the improved booth algorithm [3]). The compression of partial products can be a regular adder array, or a special tree structure (such as a wallace tree [4]). The final adder chain can directly use the chain ripple carry structure when the scale of the multiplier is small, and other high-speed carry chain structures (such as the carry selection adde...

AI Technical Summary

Problems solved by technology

[0003] In the design of large-scale integrated circuits, although the tree structure multiplier has the advantages of small area and fast speed, its irregularity makes it very difficult to design high-quality layouts.

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