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Reconfigurable 2D (two-dimensional) mesh on-chip network structure and reconfiguration method thereof

An on-chip network structure and reconfiguration technology, applied in data exchange networks, digital transmission systems, electrical components, etc., can solve problems such as topology differences, and achieve moderate hardware overhead and low power consumption.

Active Publication Date: 2012-10-24
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to solve the problem that although the virtual topology of the existing 2D mesh structure is the same as the original topology after reconfiguration, the underlying network topology is very different from the original topology, and to provide a reproducible Configured 2D mesh network-on-chip structure and its reconfiguration method

Method used

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  • Reconfigurable 2D (two-dimensional) mesh on-chip network structure and reconfiguration method thereof
  • Reconfigurable 2D (two-dimensional) mesh on-chip network structure and reconfiguration method thereof
  • Reconfigurable 2D (two-dimensional) mesh on-chip network structure and reconfiguration method thereof

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specific Embodiment approach 1

[0024] Specific implementation mode one: combine figure 1 Describe this embodiment, the reconfigurable 2D mesh network-on-chip structure described in this embodiment, the reconfigurable 2D mesh network-on-chip structure, which includes M×N cores and (M+1)×(N+1) routers, M×N cores include K×L working cores, and redundant cores (M×N-K×L);

[0025] Each core can be connected to one of the four adjacent routers: each router communicates with the four adjacent cores through the multiplexer MUX and the network interface NI.

specific Embodiment approach 2

[0026] Specific implementation mode two: combination figure 2 This embodiment is described. This embodiment is a further limitation of the reconfigurable 2D mesh network-on-chip structure described in Embodiment 1. The network interface NI includes a bus interface, a write FIFO module, a read FIFO module, unpacking and packaging The module and the control register are characterized in that the control register also includes a reconfiguration register, and the reconfiguration register includes a reconfiguration status register REC_STA, a reconfiguration control register REC_CNTL and a virtual node number register NODE_NUM,

[0027] The unpacking and packaging module is used for unpacking or packaging normal messages in the network, and is also used for packaging or unpacking reconfiguration messages, and writes the reconfiguration messages after packaging or unpacking into the reconfiguration status register REC_STA;

[0028] The reconfiguration status register REC_STA is used...

specific Embodiment approach 3

[0032] Embodiment 3: This embodiment is a further limitation of the reconfigurable 2D mesh network-on-chip structure described in Embodiment 1.

[0033] The header flake format of the network interface NI is:

[0034]

[0035]

[0036] In this embodiment, the format of the traditional network interface header chip is modified, and bits 31-29 of the service type are modified. On the basis of the original BE service and GS service, the reconfiguration service type (RC) is added.

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Abstract

The invention provides a reconfigurable 2D (two-dimensional) mesh on-chip network structure and a reconfiguration method thereof. The problem that the conventional 2D mesh structure has a virtual topological structure which is the same as an original topological structure after being reconfigured, but has a network topological structure at a bottom layer which is greatly different from the original topological structure can be solved. Each core of the reconfigurable 2D mesh on-chip network structure can be connected with one of four routers which are adjacent to the core; and each router communicates with the four adjacent cores through a multiplexer MUX and network interfaces NI. The reconfiguration method based on the structure comprises the following steps: the routers communicate with the cores according to a connection state of each router and the corresponding core in a selected sub-network; and furthermore, each core only communicates with one router at the same time. The reconfiguration method provided by the invention is used for reconfiguring the 2D mesh on-chip network structure.

Description

technical field [0001] The invention relates to a reconfigurable 2D mesh on-chip network structure and a reconfiguration method thereof. Background technique [0002] With the advancement of semiconductor manufacturing technology, multi-core chips and multi-core-based parallel computing have become new means to improve chip performance. However, as the density of transistors on a chip increases and the characteristic line width becomes smaller and smaller, the requirements for the production of single-core chips become higher and higher, and the difficulty becomes more and more difficult. A widely used solution is to introduce fault-tolerant technology in the chip design and manufacturing process. As a simple fault-tolerant scheme, redundant fault-tolerance has been rapidly developed and applied in the field of chip design. Previous work mainly focused on redundant fault tolerance at the microarchitecture level, which is more applicable when the number of cores is small. ...

Claims

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Application Information

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IPC IPC(8): H04L12/56
Inventor 付方发王晓禹王进祥吴子旭马健欣张继元
Owner HARBIN INST OF TECH
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