Method, device and system for scheduling in multiprocessor nuclear system

A technology of multi-processor cores and processor cores, applied in multi-programming devices, transmission systems, electrical digital data processing, etc., can solve unfavorable multi-processor cores, improve system efficiency, and cannot provide processor core scheduling solutions, etc. problems to meet real-time processing requirements and improve efficiency

Active Publication Date: 2014-12-24
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] When implementing the above technical solution, the inventors found that the prior art has at least the following problems: Static configuration refers to manual configuration before the system is put into operation. During the actual operation of the system, processor core scheduling according to the static configuration solution may It cannot meet the needs of real-time network I / O processing, and cannot provide a reasonable processor core scheduling scheme, which is not conducive to the improvement of the efficiency of the entire multi-processor core system

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  • Method, device and system for scheduling in multiprocessor nuclear system
  • Method, device and system for scheduling in multiprocessor nuclear system
  • Method, device and system for scheduling in multiprocessor nuclear system

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Embodiment 1

[0048] An embodiment of the present invention provides a method for scheduling processor cores in a multi-processor core system, such as figure 1 shown, including the following steps:

[0049] 101. During operation of a multiprocessor core system, acquire a first control parameter, a second control parameter, a third control parameter, and a fourth control parameter.

[0050] Wherein, the first control parameter is indication information of N data streams, and the N data streams are sorted from the most to the least in the number of data packets processed by the multi-processor core system in the first sampling period, Quantity is the data flow to which the first N data packets belong in the sorting, where N is a positive integer. Through the indication information of the N data streams, it may be known which N data streams are indicated by the indication information.

[0051] The second control parameter is the time used for each data flow in the internal transmission of th...

Embodiment 2

[0064] An embodiment of the present invention provides a method for scheduling processor cores in a multi-processor core system, such as figure 2 As shown, the method includes:

[0065] 201. During operation of a multi-processor core system, acquire a first control parameter, a second control parameter, a third control parameter, and a fourth control parameter.

[0066] Wherein, the first control parameter is indication information of N data streams, and the N data streams are sorted from the most to the least in the number of data packets processed by the multi-processor core system in the first sampling period, Quantity is the data flow to which the first N data packets belong in the sorting, where N is a positive integer. Through the indication information of the N data streams, it may be known which N data streams are indicated by the indication information. For example, when N is 3, the indication information of N data flows is: (flow1, flow5, flow6), which is used to ...

Embodiment 3

[0129] An embodiment of the present invention provides a device for scheduling processor cores in a multi-processor core system, such as Figure 5 As shown, it includes: a control parameter acquisition unit 51 , a first detection unit 52 , an inter-core switching scheduling unit 53 , and an intra-core switching scheduling unit 54 .

[0130] The control parameter acquisition unit 51 is configured to acquire a first control parameter, a second control parameter, a third control parameter and a fourth control parameter during the operation of the multi-processor core system.

[0131] Wherein, the first control parameter is indication information of N data streams, and the N data streams are sorted from the most to the least in the number of data packets processed by the multi-processor core system in the first sampling period, Quantity is the data flow to which the first N data packets belong in the sorting, where N is a positive integer. Through the indication information of th...

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Abstract

The present invention discloses a method, an apparatus, and a system for scheduling a processor core in a multiprocessor core system, which relate to the field of multiprocessor core systems, and can meet the demand for real-time network I / O processing, thereby improving the efficiency of the overall multiprocessor core system. The method for scheduling a processor core in a multiprocessor core system includes: obtaining, in the running process of the multiprocessor core system, a first control parameter, a second control parameter, a third control parameter, and a fourth control parameter; transferring a packet of a data flow that enters the multiprocessor core system to an idle processor core for processing based on the first control parameter, the second control parameter, and the third control parameter; and switching over the processor core in the multiprocessor core system between an interruption mode and a polling mode based on the fourth control parameter. The present invention is mainly applied to schedule a processor core.

Description

technical field [0001] The invention relates to the field of multi-processor core systems, in particular to a method, device and system for scheduling processor cores in a multi-processor core system. Background technique [0002] At present, services integrated on a multi-processor core system are gradually increasing, and network I / O (input / output, input / output) requests are also increasing day by day. The data processing ability of the multi-processor core system to the network I / O request becomes the key to the full performance of the system. In the prior art, a method for processing network I / O requests is: according to a statically configured processing mode, tasks are bound to specified processor cores for execution, or tasks are evenly allocated to relatively idle processor cores Another processing method is: according to the statically configured switching rules, the processor core is switched between the interrupt mode and the polling mode, thereby improving the p...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/50G06F15/177
CPCH04L47/2441G06F9/4881G06F9/4812G06F9/505
Inventor 余加强郑伟
Owner HUAWEI TECH CO LTD
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