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Integrated circuits with series-connected inductors

A technology of integrated circuits and inductors, applied in the direction of inductors, fixed inductors, circuits, etc., can solve the problem of consuming the surface area of ​​integrated circuits

Active Publication Date: 2015-05-27
ALTERA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Achieving these goals simultaneously is challenging
For example, conventional inductors exhibiting large inductance values ​​may consume excessive surface area on integrated circuits

Method used

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  • Integrated circuits with series-connected inductors
  • Integrated circuits with series-connected inductors
  • Integrated circuits with series-connected inductors

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0068] Additional Embodiments 1. An integrated circuit inductor formed in a dielectric stack comprising:

[0069] a first loop comprising at least one 45° bend; and

[0070] A second loop including at least one 45° bend, the first and second loops coupled in series and formed in respective layers of the dielectric stack.

Embodiment 2

[0071] Additional embodiment 2. The integrated circuit inductor of additional embodiment 1, wherein the first loop is nested within the second loop such that the first loop and the second loop Do not overlap.

Embodiment 3

[0072] Additional embodiment 3. The integrated circuit inductor of additional embodiment 1, wherein the first loop is laterally offset with respect to the second loop such that the first and second loops are at least partially disjoint stack.

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Abstract

An integrated circuit inductor may have upper and lower loop-shaped line portions that are connected in series. The upper and lower portions may have 45° bends that form hexagonal or octagonal loops. Each loop portion may have one or more turns. Intervening metal-free regions of metal routing layers may be formed between the two layers to reduce capacitive coupling. Each loop portion may have sets of two or more metal lines shorted in parallel by vias. The upper and lower loops may be laterally offset or nested to reduce capacitive coupling.

Description

[0001] This application claims priority to US Patent Application 12 / 721,402, filed March 10, 2010, which is hereby incorporated by reference in its entirety. technical field [0002] The present invention relates generally to integrated circuits, and more particularly to integrated circuits with inductors. Background technique [0003] Integrated circuits often have circuits such as wireless communication circuits using inductors. Inductors are typically formed using conductive traces arranged in various layers on an integrated circuit. [0004] Inductors formed on integrated circuits are characterized by inductance value and quality factor. The inductance value depends on parameters such as the length of the conductive line and the number of turns in the loop. The quality factor depends on the resistance and coupling effects of the conductive lines. [0005] As integrated circuit manufacturing technology advances, integrated circuit components are being scaled down to ev...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01Q1/24H01Q1/38
CPCH01F17/0013H01F2017/0046H01F2017/0086H01L23/5227
Inventor 陈淑鲜J·T·瓦特
Owner ALTERA CORP