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Synchronous clock extraction method for receiving end in fully digital spread spectrum communication system

A technology of spread spectrum communication and synchronous clock, which is applied in the field of full digital spread spectrum, can solve the problems such as the clock cannot be synchronized, and achieve the effect of eliminating clock signal glitches

Inactive Publication Date: 2014-08-27
BEIJING UNIV OF POSTS & TELECOMM
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But even removing most of the phase uncertainty, there is a lot of uncertainty that keeps the clocks out of sync

Method used

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  • Synchronous clock extraction method for receiving end in fully digital spread spectrum communication system

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Embodiment Construction

[0019] The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0020] Such as figure 1 As shown, the present invention provides a synchronous clock extraction method at the receiving end in an all-digital spread spectrum communication system, comprising the following steps:

[0021] S1, the sending end transmits the original data after 15 times of spread spectrum; the implementation method of the spread spectrum is: the sender encodes each bit in the original data through FPGA, and becomes the PN code whose sequence length is N Or the inverse code of the PN code whose sequence length is N, the PN code or the inverse code of the PN code represent the "0" bit and the "1" bit in the original data, and N can flexibly change the spreading...

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Abstract

The invention relates to the field of fully digital spread spectrum and discloses a synchronous clock extraction method for a receiving end in a fully digital spread spectrum communication system. The received data and PN codes or reverse codes of the PN codes are subjected to autocorrelation operation respectively at the receiving end, the obtained value of the clock signal frame-clk0 can serve as the end mark when the receiving end receives a complete spreading code in case of the absence of noise in the channel, and the complete spreading code refers to the spread data received in an original bit clock period; however, when the data are transmitted in the channel with noise, severe burr phenomena exist in the frame-clk0, the frame-clk0 cannot accurately serve as a synchronous clock of a receiving end decoding module, the coarse clock signal frame-clk0 containing burrs is subjected to repeated shift addition processing to obtain an accurate clock signal frame-clk so as to serve as a synchronous clock of the spread spectrum receiving end through the programmability of a field programmable gate array (FPGA), and the decoding error phenomenon caused by the asynchronous clock can be avoided.

Description

technical field [0001] The invention relates to the field of all-digital spread spectrum, in particular to a method for extracting a synchronous clock at a receiving end in a full-digital spread spectrum communication system. Background technique [0002] With the rapid development of modern communication technology, people pay more and more attention to the confidentiality and anti-noise performance of communication. Therefore, spread spectrum technology has been developed. In civil communication and military communication, spread spectrum communication is widely used, and it is also the core technology in the current third-generation mobile communication standard. FPGA has the advantages of rich logic units, high integration and flexible configuration, and is widely used in algorithm implementation and product prototype verification. The spread spectrum communication system needs to complete fast and complex signal processing, and the FPGA with high-speed processing capa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04B1/7073
Inventor 张民焦璐韩大海罗鹏飞
Owner BEIJING UNIV OF POSTS & TELECOMM
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