Command cancel-based cache production line lock-step concurrent execution method

Abstract

The invention discloses a command cancel-based cache production line lock-step concurrent execution method, which is implemented through the following steps of: (1) performing lock-step concurrent execution by a consistency engine and a last-level cache according to a beat number appointed by a production line and receiving a message from a consistency cache respectively; (2) judging, by the consistency engine, whether the message hits the consistency cache, and judging, by the last-level cache, whether the message hits the last-level cache; and (3) judging, by the consistency engine, whether the last-level cache is required to be accessed, transmitting, by the consistency engine, a command confirmation signal to the last-level cache if the last-level cache is required to be accessed, allowing the last-level cache to access an off-chip memory, if the last-level cache is not required to be accessed, transmitting, by the consistency engine, a command cancel signal to the last-level cache to prevent the last-level cache from accessing the off-chip memory. The command cancel-based cache production line lock-step concurrent execution method has the advantages of low access and storage delay and high access and storage performance.

Description

technical field [0001] The invention relates to an optimization method for memory access performance improvement in microprocessors, in particular to a partial pipeline execution of a hidden end-level cache (Last-Level Cache, abbreviated as LLC), which reduces the access delay for those who really need to access the end-level cache. A cache pipeline lock-step concurrent execution method based on command cancellation to improve the performance of memory components. Background technique [0002] The terminal cache in the processor can enter coherency management, such as Intel's Nehalem processor; in addition, it does not need to enter coherency management. For the end cache that does not enter the consistency management, if it has a multi-level cache hierarchy, and if the upper-level cache enters the consistency management, a coherence engine will be needed to maintain the consistency of the upper-level cache sex. [0003] Currently, there are two typical approaches to the e...

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Problems solved by technology

[0004] The disadvantage of the sequential pipeline scheme is that the pipeline of the end cache must wait until the pipeline of the consistency engine is processed before starting, which increases the delay on the memory access path; while in the parallel pipeline scheme, the memory access decoded by the end cache The request may be an invalid request, and its execution result will be canceled by the consistency engine, thus wasting memory access bandwidth in vain

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