Data path fragmentation redundancy protection structure

Abstract

The invention relates to fault tolerance protection structure of a data path component of a network-on-chip fault-tolerated route. The component with larger cost can be firstly fragmented and then redundancy backup is carried out to the fragments so as to reduce the area cost due to reliability increase. When a certain fragment is in fault, the fragments used by the data component start descend downward in sequence from the faulted fragment, and the final path of data is transmitted by the redundancy fragments. Data use fragments are controlled by two groups of multipath selector networks, the control signals of the multipath selectors are controlled by a fragment gate controller module, the module receives fragment fault information transmitted by a fragment state indicator module, then generates the control signal of the multipath selectors, and data selects proper fragment transmission data according to the gate conditions of the multipath selectors. Single fragment is large in fault probability, so that the fault-tolerated route is just suitable for the fault condition, and can ensure that the network-on-chip performances have no any loss.

Description

technical field [0001] The invention relates to the technical field of on-chip network reliability design, and relates to a redundant backup structure of on-chip router data path components. Background technique [0002] With the development of VLSI technology, more and more on-chip processing units (storage units, signal processing units, input and output units) will be integrated on the same die. Network-on-Chip (NoC) has gradually become the main standard for on-chip interconnection due to its good scalability and high throughput. As chips continue to expand in size and integration, NoC components are subject to two types of errors: (1) transient errors and (2) permanent errors. These errors can reduce chip yield and affect the efficiency and reliability of on-chip interconnects. [0003] Since the on-chip network can be regarded as the interconnection structure of a group of structured routers, the on-chip router is responsible for network flow control and routing calc...

AI Technical Summary

Problems solved by technology

Although this design can reduce the area overhead to a certain extent, it does not consider the impact on performance when the number of shard failures increases

This design severely degrades the throughput of the datapath components when the number of shard failures is high

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