High data volume FPGA (Field Programmable Gate Array) simulating testing method based on time sharing multiplex

A time-sharing multiplexing and simulation testing technology, applied in electrical testing/monitoring, general control systems, instruments, etc., can solve problems such as insufficient memory for large-data FPGA simulation testing, reduce PC dynamic memory allocation, and improve port usage Efficiency, the effect of improving the efficiency of use

Inactive Publication Date: 2013-01-02
北京京航计算通讯研究所
View PDF1 Cites 7 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is in order to solve the problem of insufficient memory of large data volume FPGA simulation test, in order to improve the adequacy of large data volume FPGA simulation test, a kind of application time-division multiplexing technology is provided to carry out the method for FPGA simulation test

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • High data volume FPGA (Field Programmable Gate Array) simulating testing method based on time sharing multiplex
  • High data volume FPGA (Field Programmable Gate Array) simulating testing method based on time sharing multiplex
  • High data volume FPGA (Field Programmable Gate Array) simulating testing method based on time sharing multiplex

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0031] Below in conjunction with accompanying drawing and embodiment, a kind of FPGA emulation test method based on time-division multiplexing provided by the present invention is further described:

[0032] Such as figure 2 As shown, a large amount of data FPGA simulation test method based on time-division multiplexing comprises the following steps:

[0033] Step S1: reduce the memory resource (mem_need) used by the simulation test to within the capacity allowed by the simulation tool;

[0034] Step S2: divide the RAM data to be tested into several parts according to the size of the memory resource, wherein the capacity of each part shall not exceed the size of the memory resource;

[0035] Step S3: using time-division multiplexing to test the divided RAM data parts respectively;

[0036] Step S4: During time-division multiplexing, use a method of dynamically managing memory to allocate and release memory by dynamically calculating the system memory space required by the c...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention belongs to the field of testing technology of programmable logic element and particularly relates to a high data volume FPGA (Field Programmable Gate Array) simulating testing method based on time sharing multiplex, and aims to solve the problem that the high data volume FPGA simulating test is insufficient in internal memory and improves the sufficiency of the high data volume FPGA simulating test. The high data volume FPGA simulating testing method comprises the step of reducing the internal memory source used for the simulating test within the allowable capacity range of a simulating tool, dividing the RAM (Random Access Memory) data to be tested into a plurality of parts based on the volume of the internal memory source, testing the plurality of divided RAM data through a time sharing multiplex way, and dynamically calculating the internal memory space of a system as current simulating requirement through an internal memory dynamic managing method, and distributing and releasing the internal memory.

Description

technical field [0001] The invention belongs to the technical field of programmable logic device testing, and relates to a large-data-volume FPGA simulation test method based on time-division multiplexing, in particular to a method of "time-division multiplexing" and "simulation" applied to large-volume FPGAs. (Field Programmable Gate Array, Field Programmable Gate Array) test method. Background technique [0002] As FPGA is widely used in aviation, aerospace, weapons and other products, its testing work is becoming more and more important. However, due to the limitations of simulation tools, for the increasingly complex FPGA data processing software, it is difficult to test the correctness of large data processing by using conventional simulation testing methods. The large amount of data in FPGA usually refers to the situation where the amount of data processed by FPGA occupies more than 50% of PC memory. [0003] The development process of a programmable logic device pro...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): G05B17/02G05B23/02
Inventor 王栋张国宇刘军刘伟郑金艳杨楠李丽华毕文敬田彪彭鸣张清陈朋赵静荣高峰
Owner 北京京航计算通讯研究所
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products