Method of fabricating ultra-low dielectric constant layer

Abstract

The invention discloses a manufacturing method for a layer with ultralow dielectric constant. The method comprises the following steps: depositing a layer with low dielectric constant on a metal layer of a silicon wafer and forming a photoetching adhesive layer with patterns of grooves and through holes on the layer with low dielectric constant through a photoetching way; etching the layer with low dielectric constant to form grooves and through holes by taking the photoetching adhesive layer as a mask; removing the photoetching adhesive layer by using wet cleaning process, depositing metal in the grooves and the through holes, then burnishing the metal to the surface of the layer with low dielectric constant and forming metal connecting lines in the layer with low dielectric constant; and performing ultraviolet irradiation on the layer with low dielectric constant for forming the layer with ultralow dielectric constant. According to the method provided by the invention, a dielectric constant material in the manufactured layer with ultralow dielectric constant can be prevented from moving.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor devices, in particular to a method for manufacturing an ultra-low dielectric constant layer. Background technique [0002] During the fabrication of semiconductor devices, interlayer dielectrics need to be fabricated. The interlayer dielectric acts as a dielectric material between metal layers and between the first metal layer and the silicon substrate of the semiconductor device. Usually, the interlayer dielectric is made of silicon dioxide, but the parasitic resistance is relatively high, which will affect the performance of the final semiconductor device. Especially with the development of semiconductor technology, the feature size of semiconductor devices is getting smaller and smaller. This situation is getting worse. Therefore, a low dielectric constant layer that can reduce the parasitic resistance value is added on the dielectric layer. The low dielectric constant layer uses lo...

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Problems solved by technology

[0013] It can be seen from the above process that since the ultra-low dielectric constant layer 12' has a porous structure, that is, the structure is relatively sparse, comparisons will be made to the ultra-low dielectric constant layer 12' with a sparse structure during etching, PVC and CMP. large impact, resulting in the migration of the dielectric constant material, and the migration of the dielectric constant material will increase the parasitic resistance value of the ultra-low dielectric constant layer 12', which will eventually reduce the performance of the fabricated semiconductor device

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