Semiconductor package and method of fabricating the same

Abstract

A semiconductor package and a method of fabricating the same. The semiconductor package includes a dielectric layer having opposite first and second surfaces; a semiconductor chip disposed on the first surface; at least two conductive pads embedded in and exposed from the first surface of the dielectric layer, and electrically connected to the semiconductor chip; a plurality of ball-implanting pads formed on the second surface of the dielectric layer; and a plurality of conductive pillars formed in the dielectric layer, each of the conductive pillars having a first end electrically connected to one of the ball-implanting pads and a second end opposing the first end and electrically connected to one of the conductive pads. Through the installation of the conductive pillars, it is not necessary for the ball-implanting pads to be associated with the conductive pads in position, and the semiconductor package thus has an adjustable ball-implanting area, so that wiring is more flexible.

Description

technical field [0001] The present invention relates to a semiconductor package, in particular to a semiconductor package that makes wiring more flexible and a manufacturing method thereof. Background technique [0002] With the evolution of semiconductor technology, semiconductor products have developed different packaging product types. In order to pursue the lightness, thinness and shortness of semiconductor packages, a quad flat no leads (QFN) packaging technology has been developed. It is characterized in that the guide pin does not protrude from the surface of the colloid. [0003] Such as figure 1 As shown, it is the circuit structure of the QFN package disclosed in US Patent No. 7,795,071, which forms an insulating layer 14 covering one side of the opening 100 on the carrier board 10 having a through opening 100, and the insulating layer 14 has an exposed On the crystal side 14a of the opening 100 and the opposite ball planting side 14b, a plurality of electrical c...

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Problems solved by technology

[0004] However, in the existing circuit structure, the positions of the ball planting pad 15 and the electrical contact pad 12 are the same (central alignment), so that the solder ball layout (solder ball layout) and the position of the electrical contact pad 12 need to cooperate with each other, resulting in Contain each other, so the ball planting area A' of the ball planting pad 15 is limited (its width is about 230 μm) and cannot be increased, thus reducing the bonding force of the solder balls

[0005] In addition, the ball planting distance b' between each of the ball planting pads 15 is about 500 μm, and the position of the electrical contact pads 12 needs to match the ball planting pads 15, so each of the electrical contact pads 12 (diameter length d' is about The pitch of 290 μm) also needs to match the ball planting distance b' of each of the ball planting pads 15, and the distance between each of the electrical contact pads 12 cannot be increased, resulting in a limited number of conductive traces 11 (lines of the conductive traces 11 The width w' and the line spacing t' are about 40μm), and there are at most two conductive traces 11 as shown in the figure, so it is difficult to increase the wiring density

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