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Lookup-table based method for parallel encoding of QC-LDPC (quasi-cyclic low-density parity-check) codes in CMMB system

An encoder and code rate technology, applied in the field of parallel implementation of QC-LDPC code encoders, can solve the problems of high equipment cost, high power consumption, multiple logic resources, etc., to reduce resource requirements, hardware cost and power consumption Effect

Inactive Publication Date: 2013-02-13
苏州威士达信息科技有限公司
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Problems solved by technology

When implemented by FPGA, more logic resources are required, which will inevitably result in high equipment cost and high power consumption

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  • Lookup-table based method for parallel encoding of QC-LDPC (quasi-cyclic low-density parity-check) codes in CMMB system
  • Lookup-table based method for parallel encoding of QC-LDPC (quasi-cyclic low-density parity-check) codes in CMMB system
  • Lookup-table based method for parallel encoding of QC-LDPC (quasi-cyclic low-density parity-check) codes in CMMB system

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Embodiment Construction

[0014] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

[0015] QC-LDPC code is a special kind of LDPC code, its generator matrix G QC and check matrix H QC Both are arrays composed of cyclic matrices and have the characteristics of segmented cyclic, so they are called quasi-cyclic LDPC codes. From the perspective of rows, each row of the circulatory matrix is ​​the result of the previous row (the first row is the last row); from the perspective of columns, each column of the circulatory matrix is ​​the result of the previous column (the first row is the last row). column) the result of circularly shifting down one bit. The set of row vectors of a circulant matrix is ​​exactly the same as the set of column vectors. Therefore, a circulant matrix can be completely characterized by its first row or column. The generator matrix G of QC-LDPC code QC It...

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Abstract

The invention relates to a solution to parallel encoding of two kinds of different QC-LDPC (quasi-cyclic low-density parity-check) codes in a CMMB (China mobile multimedia broadcasting) system. The solution is characterized in that a parallel QC-LDPC code encoder of the system mainly comprises four parts including a register, lookup tables, a bc-bit two-input exclusive-or gate and a b-bit two-input exclusive-or gate. The parallel QC-LDPC code encoder provided by the invention is compatible with multiple code rates, can fully use the functions of the lookup tables in the FPGA (field programmable gate array) logic resources to reduce the resource demand effectively under the condition of keeping the encoding speed unchanged, and has the advantages of being easy to control, consuming few resources and power, being low in cost, etc.

Description

technical field [0001] The invention relates to the field of mobile multimedia broadcasting, in particular to a parallel implementation method of a QC-LDPC code encoder in a CMMB system. Background technique [0002] Since various distortions and noises in the transmission channel will interfere with the transmitted signal, bit errors in the digital signal will inevitably occur at the receiving end. In order to reduce the bit error rate, channel coding technology needs to be adopted. [0003] Low-Density Parity-Check (Low-Density Parity-Check, LDPC) codes have become a research hotspot in the field of channel coding because of their excellent performance of approaching the Shannon limit. The quasi-cyclic LDPC code (Quasic-LDPC, QC-LDPC) code is a special LDPC code, and its coding can be realized by using a Shift-Register-Adder-Accumulator (SRAA). [0004] The SRAA method uses the generator matrix G QC to encode. The generator matrix G of QC-LDPC code QC It is composed o...

Claims

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Application Information

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IPC IPC(8): H03M13/11
Inventor 张鹏杨霏刘昌银焦玮
Owner 苏州威士达信息科技有限公司