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Lift-off method for maskless lithography

A technology of maskless lithography and lift-off process, applied in the field of semiconductor integrated circuits, which can solve the problems of low yield and long processing time

Active Publication Date: 2016-04-20
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, existing maskless lithography processes also suffer from disadvantages such as longer processing time and lower throughput
Thus, while existing maskless lithography processes are often adequate for the intended purpose, they are not fully satisfactory in all respects.

Method used

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  • Lift-off method for maskless lithography
  • Lift-off method for maskless lithography
  • Lift-off method for maskless lithography

Examples

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Embodiment Construction

[0035] It is understood that the following invention provides many different embodiments, or examples, for implementing different components of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course these are merely examples and are not intended to be limiting. For example, the following description of a first component formed on a second component may include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components are formed between the first and second components. Embodiments such that the first and second components are not in direct contact. In addition, the present invention may repeatedly refer to numerals and / or letters in various examples. This repetition is for brevity and clarity and does not in itself dictate a relationship between the various embodiments and / or structures described.

[0036] A...

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PUM

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Abstract

The invention discloses a stripping method of maskless lithography. The present invention relates to a method of implementing a maskless lithography process. The method includes receiving a computer layout file for an integrated circuit (IC) device. The layout file includes multiple IC sections. The method includes dividing the computer layout file into a plurality of sub-files. The method includes using a plurality of computer processors to simultaneously separate a plurality of subfiles, thereby generating a plurality of separate subfiles. The method includes transferring a plurality of separate subfiles to a maskless lithography system.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits. Background technique [0002] The semiconductor integrated circuit (IC) industry has undergone rapid development. Technological advances in IC materials and design have produced multiple IC eras, where each era has smaller and more complex circuits than the previous era. However, these advances have increased the complexity of handling and manufacturing ICs, and similar developments in IC processing and manufacturing are required for advances to be realized. During the evolution of integrated circuits, functional density (ie, the number of interconnected devices per chip area) has generally increased while geometry size (ie, the smallest component (or line) that can be created using a fabrication process) has decreased. [0003] In order to achieve greater functional density and shrinking geometry for semiconductor devices, various advanced photolithographic techniques have been...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/027G06F17/50
CPCG03F7/70425H01J37/3174G03F7/70433G03F7/70491H01L21/0274
Inventor 王宏钧林子钦郑年富陈政宏黄文俊刘如淦
Owner TAIWAN SEMICON MFG CO LTD