DCM (data communications multiplexer) automatic resetting method in satellite-borne high-speed modulator coding FPGA (field programmable gate array)

Abstract

The invention relates to a DCM (data communications multiplexer) automatic resetting method in satellite-borne high-speed modulator coding FPGA (field programmable gate array). The method comprises the following steps that (1) input clock clkin using a DCM module generates count of a main counter, the counting range is 0 to T, and the count is circulated after being triggered by the clkin; (2) when the count is equal to 0, the input clock clkin using the DCM module generates count_test of a clock interpretation counter, in addition, when the count is equal to, the count_test is cleared to zero, and meanwhile, reset signals rst is set to 0; (3) the count of the main counter starts to count from 1 to t1, input clock clkin signals are utilized for interpretation on the frequency of frequency multiplication output clock signals clkout; (4) when count is equal to t1+1 and the count_test is greater than the maximum, or the count_test is smaller than minimum or the DCM locking mark is low, the state shows that the DCM module is unlocked, reset signals rst are set to be equal to 1, and conversely, rst is equal to 0; (5) when the count is equal to t1+2 to t2, the reset signal rst is maintained; and (6) when the count is equal to t2+1 to T, the reset signal rst is equal to 0.

Description

technical field [0001] The invention relates to a DCM automatic reset design technology used in an on-board high-speed modulator coding FPGA. Background technique [0002] At present, the channel coding function in the on-board high-speed modulator is mostly realized by Xilinx FPGA, and the clock frequency synthesis function is completed by the digital clock management module (DCM) in the FPGA. [0003] Considering the strict reliability requirements of satellite products, it is necessary to determine the stability of the DCM module before application. By referring to the Xilinx VertexII series device user manual "Virtex-II Platform FPGA User Guide" (UG002), when the FPGA device is reconfigured, the input clock jitter is large, or the input clock frequency is changed, it may cause the DCM to lose lock. . However, in the actual application of the space-borne high-speed modulator, there is a mode of working rate switching, that is, the input clock frequency changes, and the ...

AI Technical Summary

Problems solved by technology

The disadvantage of this solution is that it requires cooperation between the ground and the satellite, and the delay in the operation process is large. At the same time, due to the need for cooperation between the uplink and the downlink, the complexity of the star software is increased.

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