Method for Improving Critical Dimension Uniformity of On-Wafer Gate Lithography
A technology of critical dimension and uniformity, applied in optics, opto-mechanical equipment, photoengraving process of patterned surface, etc., can solve the problems of high cost, affecting the critical dimension of photoresist profile, low efficiency, etc.
Active Publication Date: 2016-03-30
CSMC TECH FAB2 CO LTD
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[0005] However, the adjustment of these parameters will affect the size of the photoresist profile (PRprofile) and critical dimensions, and will also have a corresponding impact on the optical proximity correction (OPC). Therefore, the method for parameter adjustment in the lithography process program is costly and efficient. Low
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[0026] In order to make the objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.
[0027] In the traditional photolithography process, an anti-reflection coating (ARC) process is commonly used to reduce the standing wave effect. The dielectric anti-reflective coating (Dielectric Anti-reflective Coating, DARC) made of SiON (silicon oxynitride) is a kind of ARC, which is often used in the photolithography process of polysilicon gate. The inventors have found through research and experiments that by improving the uniformity of the dielectric anti-reflective coating on the polysilicon gate, the problem that the critical dimension of the polysilicon gate at the edge of the wafer is smaller than the design value can be effectively solved, thereby solving the edge leakage Failure problems, improve product yield.
[0028] In orde...
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Provided are a method for improving the gate photo-etching key size uniformity on a wafer and a dielectric medium anti-reflection coating. The method includes the following steps: providing a wafer and forming a gate layer on the surface of the wafer (S110); depositing SiON on the surface of the gate layer and forming a dielectric medium anti-reflection coating, with the deviation between the thickness of the dielectric medium anti-reflection coating anywhere and the target thickness being less than 2% (S120); coating a photoresist on the dielectric medium anti-reflection coating and exposing to form a photo-etching pattern for the gate (S130). The method employs an improved dielectric medium anti-reflection coating, and effectively controls and adjusts the uniformity of polysilicon gate key size by improving the uniformity of the thickness of the SiON in the dielectric medium anti-reflection coating, realizing the purpose of solving wafer edge leakage. Compared to the conventional method of adjusting a photo-etching recipe, re-plate marking or re-verification is not required, shortening the time and costs of yield improvement.
Description
【Technical field】 [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for improving the uniformity of critical dimensions of gate lithography on a wafer, and also to a dielectric anti-reflection coating. 【Background technique】 [0002] In the manufacture of complementary metal-oxide-semiconductor field-effect transistor (CMOS) chips, the polysilicon (poly) gate manufacturing process is a very important process, and the size of the polysilicon gate critical dimension (polyCD) will directly affect various electrical parameters of the device. The control of the uniformity of the critical dimensions of the polysilicon gate thus becomes very important. [0003] In a traditional 0.16 micron gate length (LG) process, the uniformity of the critical dimension of the polysilicon gate after photolithography is not good, especially at the edge of the wafer, the polysilicon gate critical dimension is more than 10nm smaller than that at the ...
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IPC IPC(8): H01L21/033H01L21/314G03F7/16
CPCH01L21/0214G03F7/091H01L21/02274H01L21/0276H01L21/28035H01L21/32139
Inventor 廖映雪杨兆宇许宗能赵志勇
Owner CSMC TECH FAB2 CO LTD