Vertical parasitic pnp transistor in silicon germanium hbt process and its manufacturing method

A PNP triode and vertical parasitic technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of low emission coefficient of PNP triode, inability to penetrate the germanium-silicon alloy carbon layer, and insufficient cut-off frequency to achieve improvement Effects of parasitic effects, area saving, and reduction in amplification factor

Active Publication Date: 2015-08-19
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, although the doping dose of the emitter region of the existing PNP triode is very large, because the energy is very small, it is impossible to break through the carbon layer in this layer of germanium-silicon alloy, causing most of the boron to be suppressed in the emitter region The region of a SiGe single crystal very close to the surface
And because the emitter region of the existing PNP transistor needs to grow a layer of metal silicide in the subsequent process, the heavily doped region of the surface of the germanium-silicon single crystal in the emitter region is mostly consumed, so that the existing The emission coefficient of the PNP transistor is very low, resulting in a low device amplification factor, and the cut-off frequency is not high enough

Method used

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  • Vertical parasitic pnp transistor in silicon germanium hbt process and its manufacturing method
  • Vertical parasitic pnp transistor in silicon germanium hbt process and its manufacturing method
  • Vertical parasitic pnp transistor in silicon germanium hbt process and its manufacturing method

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Embodiment Construction

[0041] Such as figure 1 Shown is a schematic structural diagram of a vertical parasitic PNP transistor in the silicon germanium HBT process of the embodiment of the present invention. In the silicon germanium HBT process of the embodiment of the present invention, the vertical parasitic PNP transistor is formed on the silicon substrate, and the active region is isolated by the shallow trench field oxygen 1 .

[0042] The base region 3 of the PNP transistor is composed of an N-type ion implantation region formed in the active region. The process conditions of the N-type ion implantation in the base area are as follows: the implanted impurity is phosphorus or arsenic, the energy condition is 100Kev-300Kev, and the dose is 1e14cm -2 ~1e16cm -2 .

[0043] A groove in contact with the base region 3 is formed in the shallow groove field oxygen 1 on the peripheral side of the base region 3, and the shallow groove field oxygen 1 located in the groove is removed, and the The depth ...

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Abstract

The invention discloses a vertical parasitic P-type semiconductor N-type semiconductor P-type semiconductor (PNP) transistor in a germanium-silicon hetero junction bipolar transistor (HBT) process. A germanium-silicon growth pre-definition window of a right trapezoid shape is adopted for enabling a germanium-silicon layer of an emitter region to be in a polycrystal structure so that dosage concentration of the emitter region is improved, emitting efficiency of a device is improved, and an amplification coefficient and cut-off frequency of the device are increased. As an advanced deep-hole contact process and a P-shaped artifact buried layer process are adopted and a structure of side connection is adopted by the base region, an area of an active region can be saved greatly, parasitic effect of the device can be improved, collector resistance of the device is decreased, and performance of the device is improved. The width of the active region is from 0.3 micrometer to 0.4 micrometer, and therefore the amplification coefficient of parasitic PNP of the device can be lowered. The invention further discloses a preparation method of the vertical parasitic PNP transistor in the germanium-silicon HBT process. The preparation method can be integrated with a process of the PNP transistor in the germanium-silicon HBT process, and production cost is lowered.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a vertical parasitic PNP transistor in a silicon-germanium HBT process, and also relates to a method for manufacturing a vertical parasitic PNP transistor in a silicon-germanium HBT process. Background technique [0002] In the practical application of radio frequency products, higher and higher device characteristic frequencies are required. NPN transistors, especially silicon germanium (SiGe) heterojunction transistors (HBT) or germanium silicon carbon (SiGeC) heterojunction transistors are good choices for UHF devices. And the SiGe process is basically compatible with the silicon process, so SiGe HBT has become one of the mainstreams of UHF devices. In this context, the requirements for the output device are correspondingly increased, such as having a certain current gain coefficient (not less than 15) and cut-off frequency. [0003] For the Bipo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/737H01L29/06H01L29/08H01L21/331
Inventor 陈帆陈雄斌薛恺周克然潘嘉李昊蔡莹陈曦
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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