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34results about How to "Improve parasitic effects" patented technology

Hybrid broadband power amplifier with capacitor matching network

A hybrid broadband power amplifier module design is disclosed. In a power amplifier design, low impedance transmission lines are typically needed at the input and output of the transistor to match for its optimum source and load impedance. The peripheral of the GaN (Gallium Nitride) transistor is very small due to the high power density of the GaN transistor. The transmission line, for example a microstrip line, needs to be very wide to achieve low impedance on ceramic substrates such as Alumina. The dimensional mismatch from the low impedance transmission line to the transistor causes additional parasitic effect to the matching networks and limits the bandwidth of the amplifier. Capacitor materials are typically very high in dielectric constant; hence a single layer capacitor with small dimensions equalizes to a low impedance transmission line. Selected capacitors with proper dimensions can be used as the low impedance transmission lines in the matching networks. They will have comparable width to the GaN transistor and minimize the parasitic effect. The wavelength inside the capacitor will also be very short due to the high dielectric constant; hence the matching network can be much shorter. A compact hybrid amplifier module has been built in a small package with the GaN transistor, capacitor matching networks and other necessary circuits inside. More than an octave bandwidth can be achieved with this new scheme.
Owner:CW ACQUISITION

Device for detecting parasitic ability of parasitic wasps and method for evaluating parasitic ability

PendingCN108522435AConvenienceEasy to move insectsAnimal husbandryPest controlBiology
The invention belongs to the technical field of biology, and particularly relates to a device for detecting the parasitic ability of parasitic wasps and a method for evaluating the parasitic ability.The device for detecting the parasitic ability of the parasitic wasps comprises a parasitic wasp hive and a host tank. The parasitic wasp hive and the host tank are combined and connected with each other; a ventilation hole and a feed hole are formed in the top of the parasitic wasp hive; the host tank is matched with the parasitic wasp hive, face plates on at least one surface of the host tank are ventilated, and a top plate of the host tank can be detached. The device for detecting the parasitic ability of the parasitic wasps and the method for evaluating the parasitic ability have the advantages that the combined device is convenient to assemble, detach and operate, simple in structure and low in manufacturing cost; the device is applicable to detecting the parasitic ability and parasitic effects of diversified parasitic wasps and is high in applicability; the method for evaluating the parasitic ability of the parasitic wasps can be implemented by the aid of the device, the parasitic ability of the parasitic wasps can be quickly and accurately tested by the aid of the method, accordingly, bases and technical support can be provided to realizing pest control effects by the aid ofthe parasitic wasps, and the technical problem of difficulty in monitoring and detecting the wasp breeding quality can be solved by the aid of the device and the method.
Owner:HENAN AGRICULTURAL UNIVERSITY

Secondary epitaxy method of N-type heavily-doped thin-layer gallium nitride material

The invention discloses a secondary epitaxy method of an N-type heavily-doped thin-layer gallium nitride material. The method comprises the following steps: (1) selecting an epitaxial material, and placing the epitaxial material on a base in MOCVD epitaxial growth equipment; (2) setting the pressure of a reaction chamber, heating the reaction chamber to a preset temperature in an ammonia gas atmosphere, and then continuously introducing an indium source; (3) keeping the pressure, the temperature, the indium source flow and the ammonia gas flow of the reaction chamber unchanged, and introducing a gallium source and silane; adjusting the flow of the gallium source and the indium source, setting the growth rate, and starting secondary epitaxy of the N-type heavily doped thin layer GaN material; (4) keeping the pressure, the temperature and the ammonia gas flow of the reaction chamber unchanged, closing the gallium source and the indium source, and continuously introducing silane for a period of time; and (5) closing the silane, cooling to room temperature under the protection of ammonia gas atmosphere, and taking out the secondary epitaxial material. The N-type heavily-doped thin-layer GaN material is good in surface appearance and high in crystallization quality, and ohmic contact resistance of a high-frequency GaN power device can be reduced.
Owner:NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD

A strain purified silicon substrate for semiconductor quantum computation and method of forming same

The invention discloses a strain purified silicon substrate for semiconductor quantum calculation and a forming method thereof, belongs to the technical field of semiconductors, and aims to solve theproblems that epitaxial purified silicon is greatly influenced by natural silicon isotope components of a substrate and the electron mobility of a purified silicon layer is low in the prior art. The strain purified silicon substrate comprises a natural silicon substrate, an insulating layer and a strain purification silicon layer, and tensile stress is introduced into the strain purification silicon layer. The forming method comprises the following steps: epitaxially forming a plurality of silicon-germanium buffer layers on a base substrate, gradually increasing the germanium doping concentration in the plurality of silicon-germanium buffer layers, and forming a strain purification silicon layer on the silicon-germanium buffer layers to obtain a donor substrate; providing a natural siliconsubstrate; forming an insulating layer on the donor substrate and/or the natural silicon substrate; and bonding the donor substrate with a natural silicon substrate, and removing the silicon-germanium buffer layer and the base substrate to obtain the strain purified silicon substrate. The strain purified silicon substrate and the forming method can be used for semiconductor quantum calculation.
Owner:INST OF MICROELECTRONICS CHINESE ACAD OF SCI

Feeding rice moth larvae with plastic foam as host breeding method

ActiveCN109744207BEasy to separateSearch and parasitize wellFodderCorcyra cephalonicaCereal grain
The invention discloses a method for breeding corcyra cephalonica larvae with plastic foam as hosts to breed bracon adoxophyesi mimankawa. The corcyra cephalonica larvae can be fed on the plastic foamto complete growth and development, the foam texture is light, the corcyra cephalonica larvae are easy to be separated from the foam, the foam can be better supplied to allow the bracon adoxophyesi mimankawa to search for parasitism, the parasitic effect is very good, and the reproduction efficiency is high. The plastic foam further has anti-mites and bacteriostatic effect, maintains the stability of the growth and development environment of the bracon adoxophyesi mimankawa, and further has a very good effect. In addition, a large number of plastic foam is used for replacing grain feed as a feed source and a feeding medium for the corcyra cephalonica larvae, the environmental pollutants are reduced, meanwhile, the plastic foam of environmental waste is turned into treasure, and a way to degrade the pollution of the plastic foam in the future is provided. A large number of parasitic bee sources are provided for the control of palm plant pests coconut woven moths and tirathaba rufivenawalker and the other prevention and control technology application by making further use of corcyra cephalonica larvae to breed the bracon adoxophyesi mimankawa.
Owner:ENVIRONMENT & PLANT PROTECTION INST CHINESE ACADEMY OF TROPICAL AGRI SCI

Vertical parasitic PNP transistor in silicon-germanium BICMOS (Bipolar Complementary Metal Oxide Semiconductor) technique and fabrication method

The invention discloses a vertical parasitic PNP transistor in the silicon-germanium BICMOS technique. A groove which is in contact with a base region is formed in a shallow trench field oxide around the base region, the depth of the groove is smaller than or equal to the depth of the base region, polycrystalline silicon is filled in the groove and doped with N-type dopant, the polycrystalline silicon doped with the N-type dopant is formed into an outer base region, which is in contact with the side of the base region, and a metal contact is formed on the outer base region, and leads out a base. The invention also discloses a fabrication method for the vertical parasitic PNP transistor in the silicon-germanium BICMOS technique. The vertical parasitic PNP transistor can be used as an output device in a high-speed, high-gain HBT (heterojunction bipolar transistor) circuit, so that one more type of device is provided as an option for the circuit, the area of the device can be effectively reduced, the parasitic effect of the device can be effectively decreased, the collector resistance of the PNP transistor can be effectively decreased, and the performance of the device can be effectively enhanced; and the method does not need additional process conditions, and can reduce the production cost.
Owner:SHANGHAI HUAHONG GRACE SEMICON MFG CORP

A strain purified silicon substrate for semiconductor quantum computation and forming method thereof

The invention discloses a strain purified silicon substrate for semiconductor quantum calculation and a forming method thereof, belongs to the technical field of semiconductors, and aims to solve theproblems that epitaxial purified silicon is greatly influenced by natural silicon isotope components of a substrate and the electron mobility of the purified silicon is low in the prior art. The purified silicon germanium substrate comprises a natural silicon supporting substrate, an insulating layer, a purified silicon germanium layer and a purified silicon layer which are stacked in sequence. The forming method comprises the following steps: epitaxially forming a plurality of silicon-germanium buffer layers and purified silicon-germanium layers on a base substrate to obtain a donor substrate; providing a natural silicon support substrate; forming at least one insulating layer on the donor substrate and/or the natural silicon support substrate; bonding the donor substrate with a natural silicon support substrate, and removing the base substrate and the multiple silicon-germanium buffer layers or removing the base substrate, the multiple silicon-germanium buffer layers and part of thepurified silicon-germanium layer to obtain a purified silicon-germanium substrate; and epitaxially forming a purified silicon layer on the purified silicon germanium substrate to obtain the strain purified silicon substrate. The purified silicon germanium substrate and the forming method thereof can be used for semiconductor quantum calculation.
Owner:INST OF MICROELECTRONICS CHINESE ACAD OF SCI

Vertical parasitic PNP transistor and manufacturing method thereof in germanium silicon heterojunction bipolar transistor (HBT) technology

The invention discloses a vertical parasitic PNP transistor in a germanium silicon heterojunction bipolar transistor (HBT) technology. A groove contacted with a base region is formed in shallow groove field oxygen in the circumference of the base region, the depth of the groove is smaller than or equal to that of the base region, polycrystalline silicon mixed with N type impurities is filled in the groove, a outer base region is formed by the polycrystalline silicon mixed with N type impurities, the outer base region are contacted with the base region on the sides of the base region, metal is arranged on the outer base region, and the metal is contacted with a base electrode and leads the base electrode out. The invention further discloses a manufacturing method of the vertical PNP transistor in the germanium silicon HBT technology. The vertical PNP transistor in the germanium silicon HBT technology can be used as an output component in a high speed and high gain HBT circuit, and thus one more component choice is supplied for the circuit, the size of a component, the parasitic effect of the component and the collector resistance of the PNP transistor are effectively reduced, the performance of the component is improved, and production lost can be reduced due to the fact that according to the manufacturing method of the vertical PNP transistor in the germanium silicon HBT technology, no extra technological conditions are needed.
Owner:SHANGHAI HUAHONG GRACE SEMICON MFG CORP

Vertical parasitic pnp transistor in silicon germanium hbt process and its manufacturing method

The invention discloses a vertical parasitic P-type semiconductor N-type semiconductor P-type semiconductor (PNP) transistor in a germanium-silicon hetero junction bipolar transistor (HBT) process. A germanium-silicon growth pre-definition window of a right trapezoid shape is adopted for enabling a germanium-silicon layer of an emitter region to be in a polycrystal structure so that dosage concentration of the emitter region is improved, emitting efficiency of a device is improved, and an amplification coefficient and cut-off frequency of the device are increased. As an advanced deep-hole contact process and a P-shaped artifact buried layer process are adopted and a structure of side connection is adopted by the base region, an area of an active region can be saved greatly, parasitic effect of the device can be improved, collector resistance of the device is decreased, and performance of the device is improved. The width of the active region is from 0.3 micrometer to 0.4 micrometer, and therefore the amplification coefficient of parasitic PNP of the device can be lowered. The invention further discloses a preparation method of the vertical parasitic PNP transistor in the germanium-silicon HBT process. The preparation method can be integrated with a process of the PNP transistor in the germanium-silicon HBT process, and production cost is lowered.
Owner:SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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