Simulation method and simulation system of integrated circuit

Abstract

The embodiment of the invention relates to the technical field of semiconductors, and provides a simulation method of an integrated circuit and a simulation system thereof, the simulation method is applied to a server, and the method comprises the following steps: receiving a unit list provided by a client; receiving an initial netlist provided by the client, wherein the initial netlist comprises a plurality of semiconductor devices and a connection relationship between the semiconductor devices in the unit list; importing parasitic parameter information of at least part of semiconductor devices in the unit list into the initial netlist to generate a result netlist; and simulating the integrated circuit based on the result netlist. The embodiment of the invention is at least beneficial to improving the simulation precision of simulating the integrated circuit.

Description

technical field [0001] The embodiments of the present disclosure relate to, but are not limited to, an integrated circuit simulation method and a simulation system thereof. Background technique [0002] With the continuous advancement of technology, the performance impact of parasitic effects such as parasitic capacitance on integrated circuits cannot be ignored, especially for deep sub-micron integrated circuit design. Specifically, an integrated circuit contains multiple electronic components, and each component may generate parasitic capacitance, which will affect the actual circuit. Post-simulation testing can be used to test whether the circuit containing parasitic capacitance meets the design requirements. At present, after the parasitic capacitance parameters are extracted, the extracted parasitic capacitance parameters are listed one by one in the code segment to form a flat parasitic parameter netlist for the integrated circuit to simulate. [0003] However, the ti...

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Problems solved by technology

[0003] However, the time-consuming extraction of parasitic capacitance parameters and the large file size of the parasitic parameter netlist will affect the simulation speed and simulation accuracy of the integrated circuit simulation

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