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Vertical parasitic PNP transistor in silicon-germanium BICMOS (Bipolar Complementary Metal Oxide Semiconductor) technique and fabrication method

A PNP triode, vertical parasitic technology, used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of shrinking device size, large device area, and large collector connection resistance, to reduce collector resistance, The effect of saving area and reducing production cost

Active Publication Date: 2014-08-13
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage is that the device area is large and the connection resistance of the collector is large
Since the extraction of the collector electrode in the prior art is realized through another active region adjacent to the collector region, and the other active region and the collector region need to be isolated by STI or other field oxygen, such This greatly limits the further reduction of the device size

Method used

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  • Vertical parasitic PNP transistor in silicon-germanium BICMOS (Bipolar Complementary Metal Oxide Semiconductor) technique and fabrication method
  • Vertical parasitic PNP transistor in silicon-germanium BICMOS (Bipolar Complementary Metal Oxide Semiconductor) technique and fabrication method
  • Vertical parasitic PNP transistor in silicon-germanium BICMOS (Bipolar Complementary Metal Oxide Semiconductor) technique and fabrication method

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Embodiment Construction

[0037] Such as figure 1 Shown is a schematic structural diagram of a vertical parasitic PNP transistor in a SiGe BICMOS process according to an embodiment of the present invention. In the silicon germanium BICMOS process of the embodiment of the present invention, the vertical parasitic PNP transistor is formed on the silicon substrate, and the active region is isolated by the shallow trench field oxygen 1 .

[0038]The base region 3 of the PNP transistor is composed of an N-type ion implantation region formed in the active region. The process conditions of the N-type ion implantation in the base area are as follows: the implanted impurity is phosphorus or arsenic, the energy condition is 100Kev-300Kev, and the dose is 1e14cm -2 ~1e16cm -2 .

[0039] A groove in contact with the base region 3 is formed in the shallow groove field oxygen 1 on the peripheral side of the base region 3, and the shallow groove field oxygen 1 located in the groove is removed, and the The depth o...

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Abstract

The invention discloses a vertical parasitic PNP transistor in the silicon-germanium BICMOS technique. A groove which is in contact with a base region is formed in a shallow trench field oxide around the base region, the depth of the groove is smaller than or equal to the depth of the base region, polycrystalline silicon is filled in the groove and doped with N-type dopant, the polycrystalline silicon doped with the N-type dopant is formed into an outer base region, which is in contact with the side of the base region, and a metal contact is formed on the outer base region, and leads out a base. The invention also discloses a fabrication method for the vertical parasitic PNP transistor in the silicon-germanium BICMOS technique. The vertical parasitic PNP transistor can be used as an output device in a high-speed, high-gain HBT (heterojunction bipolar transistor) circuit, so that one more type of device is provided as an option for the circuit, the area of the device can be effectively reduced, the parasitic effect of the device can be effectively decreased, the collector resistance of the PNP transistor can be effectively decreased, and the performance of the device can be effectively enhanced; and the method does not need additional process conditions, and can reduce the production cost.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a vertical parasitic PNP transistor in a silicon-germanium BICMOS process, and also relates to a method for manufacturing a vertical parasitic PNP transistor in a silicon-germanium BICMOS process. Background technique [0002] In RF applications, higher and higher device characteristic frequencies are required. BiCMOS (Bipolar CMOS) is a technology in which CMOS and bipolar devices are integrated on the same chip at the same time. In BiCMOS process technology, NPN triodes, especially silicon germanium (SiGe) heterojunction triodes (HBT) or germanium silicon carbon heterogeneous Junction triode (SiGeC HBT) is a good choice for UHF devices. And the SiGe process is basically compatible with the silicon process, so SiGe HBT has become one of the mainstreams of UHF devices. In this context, the requirements for the output device are correspondingly incre...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/732H01L21/331
Inventor 陈帆陈雄斌薛凯周克然潘嘉李昊蔡莹陈曦
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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