Rapid disconnection control circuit applied to power management circuit

Abstract

The invention relates to a rapid disconnection control circuit applied to a power management circuit. The rapid disconnection control circuit applied to the power management circuit comprises a power on reset (POR) falling edge detection circuit and a p-channel metal oxide semiconductor (PMOS) discharge tube Mp2, the POR falling edge detection circuit comprises a delay module, a phase inverter and an NAND gate, the input end of the POR falling edge detection circuit is connected with the input end of the delay module and the input end of the phase inverter, the output end of the delay module and the output end of the phase inverter are respectively connected with two input ends of the NAND gate, the output end of the POR falling edge detection circuit is connected with the output end of the NAND gate, the output end of the POR falling edge detection circuit is connected with a grid electrode of the PMOS discharge tube Mp2, a source electrode of the MPOS discharge tube Mp2 is connected with supply voltage Vdd, and a drain electrode of the PMOS discharge tube Mp2 is connected with the ground. When the rapid disconnection control circuit is applied to the power management circuit, the rapid disconnection control circuit guarantees that a hardware system is powered off in time in a disconnection process of the supply voltage, and avoids that the hardware system sends wrong instructions or executes wrong operation due to unstable states of parts of circuits under the condition of low voltage.

Description

Technical field [0001] The invention relates to a fast power-off control circuit applied in a power management circuit, and belongs to the technical field of power management control circuits. Background technique [0002] With the increasing role of power management circuits in electronic products, the performance of power circuits in electronic products is becoming more and more important. The power management circuit is used on almost every chip, which requires the power management circuit to have high indicators to extend the use time of electronic products. For example, Low Drop Voltage Regulator (LDO) is a commonly used power management circuit. A common LDO is often connected with a capacitor of a few microfarads to ensure stable operation of the circuit. However, in some cases, during the chip power-off process, due to the low current consumption of the circuit and the large voltage stabilizing capacitor at the power supply voltage terminal, the power supply voltage will...

AI Technical Summary

Problems solved by technology

However, in some cases, during the power-off process of the chip, due to the low current consumption of the circuit and the large voltage stabilizing capacitor at the power supply voltage terminal, the power supply voltage will drop very slowly, such as figure 1 shown in

As a result, during the power-off process of the power supply voltage, because the power supply voltage is already lower than the normal working voltage of the circuit, but it is not 0, some circuits will appear unstable, causing the hardware system to issue wrong instructions or execute wrong operation

Especially in application environments such as non-contact smart cards, the power supply voltage is maintained by the charge stored on the capacitor in the chip, and the power-off process will be very slow, which may easily cause logic function or storage errors of the chip during power-off

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