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Methods of fabricating fan-out wafer level packages and packages formed by the methods

A wafer-level packaging, semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as difficult to bond solder balls, difficult to manipulate and test WLP

Active Publication Date: 2013-06-19
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, it is difficult to bond the desired number of solder balls to the WLP
In addition, as the size of semiconductor chips becomes smaller, it is difficult to manipulate and test WLP

Method used

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  • Methods of fabricating fan-out wafer level packages and packages formed by the methods
  • Methods of fabricating fan-out wafer level packages and packages formed by the methods
  • Methods of fabricating fan-out wafer level packages and packages formed by the methods

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0055] Figure 1 to Figure 9 is a cross-sectional view illustrating a method of manufacturing a fan-out wafer level package according to some example embodiments of the inventive concepts.

[0056] refer to figure 1 , the receiving part CR in which the cavity CV is formed can be prepared. The receiving part CR may be a carrier or an auxiliary mold provided on the carrier. The receiving part CR may be formed of at least one of various materials such as glass, plastic, or metal. The cavity CV may be formed in the receiving part CR using a molding process, a laser process, or an etching process. In this embodiment, the cavity CV may provide a space corresponding to the size of the first semiconductor chip CP1 to be disposed in the cavity CV.

[0057] refer to figure 2 , the isolation layer IL is conformally formed on the entire surface of the receiving part CR on which the cavity CV is formed. The isolation layer IL may be a double-sided adhesive tape or an adhesive layer....

no. 2 example

[0068] Figure 10 to Figure 15 is a cross-sectional view illustrating a method of manufacturing a fan-out wafer level package according to some example embodiments of the inventive concepts.

[0069] refer to Figure 10 , preparing a receiving part CR with a cavity CV. The receiving part CR may be a carrier or an auxiliary mold provided on the carrier. The receiving part CR may be formed of at least one of various materials such as glass, plastic, and metal. One inner side wall of the cavity CV may have a stepped shape. The cavity CV may provide a space having a depth and a size capable of receiving a plurality of semiconductor chips. The isolation layer IL is conformally formed on the receiving part CR having the cavity CV. The isolation layer IL may be a double-sided adhesive tape or an adhesive layer.

[0070] refer to Figure 11 , the first to third semiconductor chips CP1, CP2 and CP3 are disposed in the cavity CV. The first semiconductor chip CP1 may include a fi...

no. 3 example

[0079] Figure 16 to Figure 20 is a cross-sectional view illustrating a method of manufacturing a fan-out wafer level package according to some example embodiments of the inventive concepts.

[0080] refer to Figure 16 , preparing the receiving part CR in which the first cavity CV1 and the second cavity CV2 are formed. The receiving part CR may be a carrier or an auxiliary mold provided on the carrier. The receiving part CR may be formed of at least one of various materials such as glass, plastic, and metal. The first cavity CV1 may serve to receive a semiconductor chip, and the second cavity CV2 may serve as a partition area between adjacent packages. The isolation layer IL is conformally formed on the receiving part CR having the first and second cavities CV1 and CV2. The first semiconductor chip CP1 is disposed in the first cavity CV1. The second semiconductor chip CP2 is then disposed on the first semiconductor chip CP1 with an adhesive layer AD in between. The seco...

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PUM

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Abstract

A fan-out wafer level package may include at least two semiconductor chips; an insulating layer covering portions of a first semiconductor chip; a mold layer covering portions of a second semiconductor chip; a redistribution line pattern in the insulating layer; and / or an external terminal on the insulating layer. The first semiconductor chip may be stacked relative to the second semiconductor chip. The redistribution line pattern may be electrically connected to the at least two semiconductor chips. The external terminal may be electrically connected to the redistribution line pattern. A fan-out wafer level package may include at least three semiconductor chips; an insulating layer covering portions of first semiconductor chips; a mold layer covering portions of a second semiconductor chip; a redistribution line pattern in the insulating layer; and / or an external terminal on the insulating layer. The first semiconductor chips may be stacked relative to the second semiconductor chip.

Description

technical field [0001] Example embodiments of inventive concepts relate to a method of manufacturing a fan-out wafer level package and / or a package formed by the method. Background technique [0002] A packaging process for manufacturing a semiconductor package refers to a series of processes for connecting a semiconductor chip to external connection terminals and sealing the semiconductor chip for protecting the semiconductor chip from external impact. [0003] With the development of the electronics industry, semiconductor packages have been variously developed for the purpose of small size, light weight, and low manufacturing cost. In addition, with widespread use in various application fields such as digital display devices, MP3 players, mobile phones, and mass storage devices, various semiconductor packages are proposed. For example, various semiconductor packages may include ball grid array (BGA) packages and wafer level packages (WLP), among others. [0004] A semic...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/683H01L21/60H01L23/498
CPCH01L23/3128H01L21/561H01L21/568H01L2224/32145H01L2224/24146H01L24/13H01L24/24H01L24/73H01L24/82H01L2224/13022H01L2224/24011H01L2224/73209H01L2224/73253H01L2224/73267H01L2224/82101H01L2224/96H01L2224/82031H01L23/5389H01L2224/04105H01L2224/12105H01L2224/131H01L2225/06586H01L25/0652H01L25/0657H01L25/50H01L2225/06524H01L2225/06562H01L2225/06568H01L2225/06548H01L2224/0401H01L2924/181H01L2924/12042H01L24/96H01L23/13H01L23/12H01L23/057H01L23/055H01L23/24H01L23/053H01L23/02H01L23/04H01L23/49575H01L23/08H01L23/4926H01L23/34H01L2224/73217H01L2924/00014H01L2224/82H01L2924/014H01L2924/00H01L2924/00012H01L23/48
Inventor 朴辰遇宋昊建李锡贤
Owner SAMSUNG ELECTRONICS CO LTD