Error correction method of memory

An error correction method and memory technology, applied in static memory, digital memory information, information storage, etc., can solve the problem of increasing the storage array area by supervisory bits, and achieve the effect of reducing the possibility of DRAM errors

Active Publication Date: 2013-07-03
XI AN UNIIC SEMICON CO LTD
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AI Technical Summary

Problems solved by technology

[0005] The invention provides an error correction method for a memory, which mainly solves the problem that in the existing ECC encoding process, due to the existence of data masking, the encoding cannot be smoothly performed to generate supervisory bits or the area of ​​the storage array needs to be increased to generate supervisory bits.

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Embodiment Construction

[0020] Combine figure 1 , The existing ECC encoding can be carried out according to the following steps:

[0021] First, 64-bit data from the outside is written directly ( figure 1 A);

[0022] Secondly, the ECC encoding circuit uses this 64-bit external data to generate 7-bit or 8-bit supervision bits ( figure 1 B);

[0023] Again, the new 64-bit data and 7 / 8-bit supervision bits are written into the storage array and completely replace the previously stored information ( figure 1 C).

[0024] Combine figure 2 , The decoding and correction of the existing ECC are carried out according to the following steps:

[0025] First, 64-bit data and 7 / 8-bit supervision bits are read from the storage array ( figure 2 C).

[0026] Secondly, the supervision bit will decode according to certain rules to determine whether the data is wrong, if there is an error, which bit is wrong and correct the wrong data ( figure 2 B).

[0027] Again, the decoded data is read out ( figure 2 A).

[0028] Combine ...

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Abstract

The invention provides an error correction method of a memory and solves the problem that a conventional ECC (error correction code) encoding process cannot be smoothly performed to achieving encoding and a parity bit cannot be generated due to existing of a data mask, or a storage array area is required to be increased in order to generate the parity bit. The error correction method of the memory comprises the following steps: (1) external data are read in, the parity bit is generated according to a set rule, a characteristic bit is generated simultaneously, and the external data, the characteristic bit and the parity bit are stored in the memory; and (2) the external data, the characteristic bit and the parity bit in the memory are read out, if characteristic bit characterizes that the data mask (DM) exists, the parity bit is invalid, and decoding and error correction are not performed when the data are read out, and if characteristic bit characterizes that the DM dose not exists, the parity bit is valid, and decoding and error correction are performed by utilizing the parity bit when the data are read out. The error correction method of the memory can reduce the possibility for a DRAM (dynamic random access memory) to make errors, even for a system using the DM.

Description

Technical field [0001] The invention relates to an error correction method of a memory. Background technique [0002] ECC (Error Correction Code) is used to detect and correct erroneous data. The data shows that there are many algorithms to support ECC. For example, the most commonly used Hamming Code, 8-bit data requires 4 parity bits, and 64-bit data requires 7 parity bits. The appropriate algorithm can be selected by the length of the data and the number of bits to be detected and corrected. [0003] For different DDR structures (DDR1 / 2 / 3), typical streamin and out data read prefetch data lengths are 32 bits, 64 bits and 128 bits. A reasonable compromise solution can use 7-bit or 8-bit supervision bits for 64-bit data (according to different ECC algorithms), such as figure 1 with figure 2 Shown. [0004] But it is not so simple for DRAM to realize the function of detection and correction, because of the existence of DM data mask. In other words, when data is written into the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/42
CPCG11C7/1009G11C29/42G11C29/52G11C2029/0411G11C29/78G06F11/1052H03M13/19G06F11/102G06F11/1048
Inventor 亚历山大
Owner XI AN UNIIC SEMICON CO LTD
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